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verilogHDL
- RS（31，15）译码关键步骤的veilog HDL算法实现，包括关键方程求解，错误位置估计，错误值计算等-RS (31,15) decoding a key step in the algorithm veilog HDL, including key equations, position estimation error, error value, such as
RX_SYN
- OFDM接收机新型同步算法的实现，采用verilogHDL语言，经测试性能良好-OFDM receiver to achieve the new synchronization algorithm, using verilogHDL language, good performance tested
RX_RS_DEC
- OFDM系统新型RS编解码的verilogHDL设计，经测试误码率性能提高-OFDM system verilogHDL new RS codec design, improved bit error rate performance tested
RS_CC_ENC
- OFDM系统新型CC编解码的verilogHDL设计，与RS编码级联，经测试误码率性能提高-OFDM system verilogHDL new CC codec design, coding and RS cascade, tested BER performance improvement