搜索资源列表
cheng
- 开放式实验，CPU的设计，乘法器实验，简单乘法器-Open experiment, CPU design, the multiplier experiment, a simple multiplier
multiply_vhdl
- 用VHDL语言设计一款带进位的5位乘法器。-Design with VHDL into a 5-bit multiplier.
Verilog_100exaples
- Verilog的100个经典设计实例，包括交通灯的设计代码，智能时钟的设计代码，各种加法器。乘法器的设计代码-100 classic Verilog design examples, including the traffic light design code, intelligent clock design code, a variety of adder. Multiplier code
Example8
- 一个基于FPGA的4位流水乘法器的小程序，设置了时钟输入，数据输入，并输出结果。-One of four water-based FPGA multiplier applet, set the clock input, data input and output.
mpy
- 在IAR环境上，验证msp430f5529的硬件乘法器，提供msp430f5529的硬件乘法器的程序示例。-On the IAR environment, verify msp430f5529 hardware multiplier, provides program examples msp430f5529 hardware multiplier.
Multi_SI
- 用verilog实现的乘法器，可以综合，经过验证。-Implementation multiplication with verilog.
mult-64bit-booth.txt
- 64位booth乘法器，verilog HDL， zip文件，modelsim测试通过-64 booth multiplier, verilog HDL, zip files, modelsim test
mux16
- 基于FPGA的verilog编写的乘法器-FPGA-based multiplier verilog prepared
multiply_verilog
- 几个常用的乘法器的verilog实现，包括普通乘法器，时序乘法器，行波乘法器-Several commonly used multiplier verilog achieve, including ordinary multiplier, multiplier timing, traveling wave multiplier, etc.
mux
- 利用velilog语言，进行乘法器的设计-velilog language, multiplier design
mux16
- 16*16位的乘法器 ， 包含仿真文件-16* 16-bit multiplier, including simulation files! ! ! ! ! ! ! ! ! !
chengfa
- 本文详细介绍了乘法器的功能和设置，便于读者学习-This paper describes the functions and settings of the multiplier, easy to readers to learn
multiply_8_VHDL
- 由8 位加法器构成的以时序方式设计的8 位乘法器，采用逐项移位相加的方 法来实现相乘的VHDL程序代码。包含几个小模块和一个顶层设计文件，运行可用。-an 8 bit multiplier combined with 8 bit adder using a design by way of timing,and it use a way of Itemized shift to implement the multiply.It include some little module and
sss
- 使用Verilog语言编写源代码.调用一些基本的IP核，如DCM模块、DDS模块ChipScope模块、乘法器模块等来实现调制.最后通过编程并利用FPGA板子实现AM、DBS、SSB的调制。-Using Verilog language source code. Invoke some basic IP cores, such as DCM module, DDS module ChipScope modules, multiplier module to achieve modulation.
32bitvhdl
- 基于硬件描述语言的通过加法器实现的32位乘法器-Hardware descr iption language implemented by the adder 32 of the multiplier
ChengFaQi_mux16
- 实现16位乘法器 并有modelsim仿真文件-The realization of the 16 bit multiplier and Modelsim simulation file!!!!!!!!!!!!!!!!!!!!!!!!
booth-mutiplier
- booth乘法器的verilog实现及仿真。 内含verilog源码和modelisim仿真源码，清晰的实现了硬件乘法器，代码注释清晰-booth multiplier verilog verilog implementation and simulation contains the source code and modelisim simulation code, clear notes
32FIRVHDL
- 基于FPGA的32阶FIR数字滤波器设计 源程序。设计使用了并行乘法器，运行速度更快，占用内存更小，延迟更小。 -32 order FIR digital filter based on FPGA design source program. Design USES parallel multiplier, faster and less memory, less delay.
MPY
- MSP430F1XX系列单片机 内部硬件乘法器 MPY应用-MSP430F1XX MPY
Multiply8-6
- FPGA verilog用移位相加的方式来实现8位的乘法器-FPGA verilog With shift and add a way to achieve 8 multiplier