搜索资源列表
chengfaqi
- 利用51单片机和按键实现乘法器的功能，按键所按数值会在串口中显示出来，并且能在串口中得到作乘法之后的结果-Use SCM and realize multiplier function keys, press the numeric keys are displayed in the serial port, and can be obtained as a result of the multiplication of the serial ports later
assignment
- 4*4乘法器，分层化，可扩展，含仿真结果，quartus12.1可用。 -4* 4 multiplier, hierarchical struction, including simulation results, quartus12.1 available.
cmp42
- 用于乘法器设计，8位Booth译码乘法器，4-2压缩结构，加速乘法运算速度-Used for the design of multiplier, 8 Booth decoding multiplier, 4-2 compressed structure, accelerate the multiplication rate
book3e
- 数字信号处理的FPGA实现随书光盘，包含大量Verilog代码，包括加法器，乘法器以及FIR滤波器设计，快速傅立叶变换-FPGA digital signal processing to achieve the CD with the book, contains a large amount of Verilog code, including the adder, multiplier and FIR filter design, fast Fu Liye transform
chengfaqi
- 数字电路中实现八位二进制乘法器的VHDL代码-Digital Circuit achieves eight binary multiplier VHCDL code
chengfaqi
- 16位的原码两位乘法器，实现原码两位乘，经试验可以使用-16 of the original code two multiplier, two implementation source code
fwdfwfft
- 4位的16点fft，ccmul为复数乘法器，bfproc为蝶形运算器，输出的结果为四位，每一级都要进行round操作。-4 16-point fft, ccmul for complex multiplier, bfproc for the butterfly operation, a result output is four, each stage should be carried out round operation.
original-1-by-16-bit-multiplier
- 原码一位乘16位乘法器 用VerilogHDL语言实现-Original code A by 16-bit multiplier VerilogHDL language used to achieve
SOC_Code
- 加法器，原码补码乘法器，ROM设计，PC计数器等的VHDL详细代码-The source-code complement adder, multiplier, ROM design, such as PC counter of VHDL code in detail
MSP430x261x_MPY
- MSP430x261x 硬件乘法器配置程序-MSP430x261x hardware multiplier configuration program
fifo_pipeline_booth_multiplier
- fifo_pipeline_modified_booth_multiplier一个使用FIFO的Booth乘法器，并且使用了流水线描述方式，本程序给予verilog 语言-fifo_pipeline_modified_booth_multiplier, a booth multiplier using pipeline technology in verilog HDL language
pipeline_lut_multiplier
- pipeline_lut_multiplier, 一个使用查找表实现的流水线乘法器，本程序使用verilog HDL language 语言编写-pipeline_lut_multiplier ，a multiplier based on look up tablets ,and it is programing in verilog language
AD9854_Template
- 本系统是基于零中频正交解调原理的简易频率特性测试仪，用于检测被测网络的幅频特性和相频特性。该系统主要包括DDS集成模块，RLC串联谐振电路，乘法器电路，低通滤波器，同相放大器和测量显示模块，其中RLC串联谐振电路作为被测网络。本系统以DDS 集成模块为核心，将其产生的正交扫频信号通过被测网络后，经乘法器得到高频信号；这两个信号经过低通滤波、同相放大后得到符合要求的I、Q直流分量；最后通过单片机进行ADC 采样、数据处理和液晶显示，得到被测网络的幅频特性和相频特性。本系统在算法上的创新之处
VHDL_Multiplier
- 三种 VHDL 实现乘法器的方法，可以用于学习FPGA的时序、组合电路，同时附带了 TestBench 程序-Three kinds of methods to achieve multiplier in VHDL, with TestBench
myfpga
- 这个是经典的FPGA的相关的乘法器，除法器的代码，还有别的可用的资料，都是网络上攒的，并且真的是非常经典-This is a classic of the relevant multiplier divider FPGA code, as well as other available information, are saved on the network, and really is very classic
multiplieranddivider
- 乘法器和除法器的VHDL实现方法,可运行，占用逻辑资源少。-VHDL descritpion about muiltiplier and divider
c5
- 加法器、乘法器、除法器、DDS函数信号发生器等FPGA实现-Some signal generator build by FPGA！
multiplier-ROM--FIFO-memory
- 布斯，阵列乘法器，加减交替除法器，以及ROM存储器，FIFO存储器-Booth, array multiplier, divider alternately add and subtract, and ROM memory, FIFO memory
booth_multiplier
- 使用verliog设计实现booth乘法器，通过modelsim仿真验证通过-Use verliog design implementation booth multiplier by simulation by modelsim
booth_multiplier_modify
- 使用verliog改进传统的booth乘法器，通过modelsim仿真验证通过-Use verliog improve the traditional booth multiplier, verified by simulation by modelsim