搜索资源列表
flexdec
- 该源代码运行于89c51系列单片机上,可从输入FLEX二进制码流中解交织,处理CRC纠错,并最终解码出有效ASCII码数据.-the source code running on 89c51 MCU, FLEX can be imported from binary code stream deinterleave handling of CRC error correction. and finally decoding of effective ASCII data.
BCH-MPS430
- c语言写的用于单片机mps430的底层通信协议，包含了bch编解码，交织编解码，和crc校验。经过简单的修改即可用于其他的单片机。-write for the MCU mps430 underlying communication protocol includes the BCH encoding and decoding, codecs are intertwined, and crc check. After a simple modifications can be used in ot
cf_interleaver2
- interleaver即交织器，里面包含有C,VHDL,VRILOG HDL三种语言写的交织器, 包括各种各样的组合达六七十种，描写详尽，是一个难得的学习交织器的材料 -interleaver that interleaver, which contains C, VHDL, VRILOG HDL three languages to write the interleaver, including a variety of combinations to depend species,
suij
- 硬件编程实现伪随机交织器和随机交织器，应用环境Quartus II5.0-hardware programming pseudo-random interleaver and random interleaver, application environment Quartus II5.0
interleaver-vhdl.rar
- VHDL编写的基于FPGA的4-8交织器代码，有需要的下来看看,4-8 prepared VHDL code interleaver
interweave_1
- 用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入，按列读出的方法实现。主要包括：信源信号产生（20位的m序列），交织器，解交织器。为实现流水线的操作，采用了两个交织器和两个解交织器，当一个写入数据的时候，另一个读出数据。-Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by colu
4_31
- 这是一个交织器/解交织器的FPGA实现，虽然交织器的功能简单，但是其实现比较复杂-This is an interleaver/de-interleaver to achieve the FPGA, although the function of interleaver simple, but its more complicated to achieve
top
- 交织的vhdl实现，希望对大家有帮助，同他学习！-VHDL-cutting to achieve, I hope all of you help with his learning!
ENCODE
- 本源码实现交织编码，源码为VHDL语言。运行于发射端FPGA。-Interleaved Coded achieve this source, source code for VHDL language. Running on the transmitter FPGA.
Turbo
- 基于fpga的交织编码器设计，主要讲叙如何在fpga上实现交织编码器。-something about turbo。
interleaver
- 通信系统中的数据交织程序The data communication system procedures intertwined-The data communication system procedures intertwined The data communication system procedures intertwined
interleaver
- 这是一个用VHDL编写的交织器程序,使用交织器能够使干扰由突发变成随机化-This is a prepared using VHDL interleaver, the use of interleaver enables interference by the sudden randomized into
interleaver
- 实现矩阵交织的Veriog源代码，内含有modelsim测试文件-Veriog interwoven matrix of the realization of the source code files containing the test modelsim
itrl
- 交织 本程序是自己编写的随机交织 可以实现任意维度 任意长度 的交织 比起其他的实现方法更具有 推广型-Intertwined in this program is to prepare its own random interleaving can achieve any arbitrary length of the intertwined dimensions of the implementation is more than the other type has the ext
CONVOLUTIONAL_INTERLEAVER
- DVB数据交织,交织深度I=12,已得到应用!-DVB data interleaving, interleaving depth I = 12, has been applied!
interleaver_Matlab_Verilog
- Matlb和verilog编的两个文件。是关于OFDM通信中的交织。-Matlb and verilog OFDM communication interleave
interlace
- 根据MATLAB中的伪随机交织器产生的交织图案初始化到ROM中，从ROM中读取交织图案对输入数据进行交织。同时也可根据解交织图案进行解交织，同样的算法。-In accordance with MATLAB generated pseudo-random interleaver initialization pattern woven into the ROM, read from the ROM interwoven interwoven pattern of input data. Can a
interweave_cordingacording
- 此文件包含交织器和解交织器的代码。实现完整的交织过程。-the code and decode of interweave.
卷积交织器解交织器设计
- 交织技术通常分为分组交织和卷积交织。分组交织过程是数据先按行写入，再按列读出；解交织过程是数据先按列写入，再按行读出。其特点是结构简单，但数据延时时间长，而且所需的存储器比较大。(Interleaving techniques are usually divided into packet interleaving and convolution interleaving. Packet interleaving process is the first data written by row,
DATA_Interleaver
- 这是交织的实现源码 可用于具体的工程实践(This is the interwoven implementation source code that can be used in specific engineering practices)