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gongcehngsheji_477-2
- 使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
coverlater
- 本程序是在Quartus7.2环境下编译的一个简单的(2,1,3)卷积码，能够成功地编译和仿真。
ViterbiDecodeK9R12HardDecision
- viterbi 硬判决译码，基本实现了（2，1，9）卷积码的硬判决译码，用modelsim RTL仿真通过-hard-decision viterbi decoding, the basic realization of the (2,1,9) convolutional codes hard decision decoding, using modelsim RTL simulation through
smldPe55_cnv
- 信号处理方面的 源代码，卷积码通信系统的蒙特卡罗仿真函数，-Signal processing, source code, convolutional code communication system of the Monte Carlo simulation function
UHF-RFID-CRC
- 本文首先研究了IsO／IECl8000．6标准中A、B两类短程通讯的前向链路与返回 链路的数据编码方式，对(FMO)双相间隔编码、(PIE)脉冲间隔编码、曼切斯特码 的编解码方式和技术参数进行了深入的分析，并利用FPGA实验平台对这三种编 码的编、解码电路进行了设计和仿真。然后对UHF RFID系统的差错控制技术原理 进行了探讨，重点研究了ISo／IECl8000．6标准中采用的数据保护与校验技术，即 循环冗余校验(CRC)技术。分析了基于线性反馈移位寄存器(LFSR)实现C
convolution
- convolution卷积码生成器程序设计及仿真源代码-convolution convolutional code generator source code of program design and simulation
INTERLEAVER
- 1/3,k=9的卷积码VHDL实现,在xilinx ise上仿真成功。-1/3, k = 9 convolutional code VHDL implementation of the simulation in the xilinx ise success.
cooperative-communication
- 一种基于卷积码的机会中继编码协作的协作通信的仿真代码，仿真误比特率-a coded cooperation cooperative communication simulation codes based on the convolutional code to acquire the bit error probability
encoding-decoding
- 卷积码编码译码程序以及其modelsim仿真波形文件等-Convolutional code encoding and decoding procedures and the Modelsim simulation waveform file
juanji1
- 本程序是在Xilinx ISE上编写的，它完成（2,1,6）卷积码的编码工作。里面有源程序和用以仿真的测试文件-The program is written on Xilinx ISE, it completed the (2,1,6) convolutional code encoding. Source and for the simulation of the test file inside
juanji2
- 本程序是在Xilinx ISE上编写的，它完成（2,1,6）卷积码的译码工作。里面有源程序和用以仿真的测试文件-The program is written on Xilinx ISE, it completed (2,1,6) convolutional code decoding. Source and for the simulation of the test file inside
conv_encode
- 本设计是一个基于FPGA的咬尾卷积码编码器设计，要求使用verilog语言编写编码器模块，通过编译和综合，并通过matlab和modelsim仿真对比验证设计结果。-The design is an FPGA-based tail-biting convolutional code encoder design requires the use verilog language encoder module, through compilation and synthesis, and by c
JJ213_program
- 卷积码（213）的编译码，VHDL语言编写的整个工程文件，带有仿真结果图。-Convolution code (213) codec, VHDL language of the whole project file with the simulation results shown in Fig.
cycle_en_decoder
- 卷积码编码/解码，Verilog语言实现，带仿真程序。-Convolution encoder/decoder, Verilog language, with a simulation program.
OFDM_Convolution
- 自己写的卷积码，能实现仿真结果,有testbench文件-Write your own convolution code, simulation results can be achieved