基于状态机编写的串口通信实验，编程语言是Verilog HDL，可发送八位数据，在Altera的EP4CE15F17C8芯片上验证成功。（与另一个发送256位不同的是这个代码比较突出状态机的使用）。-Prepared by the serial communication experiment based on state machine, the programming language is Verilog HDL can transmit eight bits of data, verif

基于verilog的串口通信接收部分代码，欢迎下载交流！-Receiving part of the code verilog based serial communication, welcome to download the exchange!

精简的verilong串口通信源码，带通信自定义模块(Streamlined verilong serial communication source code, with communication custom module)