搜索资源列表
chengxing1
- 成型滤波器的verilog代码--Verilog source code for formatted wave filter.
baseband_verilog.rar
- verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器,verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum m
BeamformingFPGA
- 波束成型，基于FPGA的波束成型，包括两个文件，一个滤波器，一个xilinx仿真-Beamforming
fir_512_378_mux
- 512阶高速FIR成型滤波器，四相位复用，树形加法和多级流水线结构。-512-order high-speed FIR shaping filter, four-phase re-use, tree addition and multi-stage pipeline structure.
Digital-filter-design
- 数字成形滤波器设计及FPGA实现 本文对数字基带信号脉冲成型滤波的应用、原理及实现进行了研究。-Digital filter design and FPGA realization of forming this paper, the digital baseband signal pulse shaping filter applications, principle and implementation were studied.
gg
- FPGA实现基带成型滤波器，升余弦滚降系数，多进制调制-FPGA
chengxing1
- 成型滤波器的verilog代码--Verilog source code for formatted wave filter. -Verilog source code for formatted wave filter
filter_lpm_shaping
- 4倍内插值的fir成型滤波器，语言vhdl，工程已建立，可以直接运行-4x interpolation of fir shaping filter, language vhdl, project has been established, you can directly run
interpolation_shaping_filter
- 内插成型滤波器的FPGA实现，可根据需要配置不同的内插倍数，Quarter II环境编译，可直接使用-Interpolation shaping filter FPGA, can be equipped with different interpolation factor, Quarter II compiler environment, can be used directly
shape
- 基于FPGA的成型滤波器的代码，里面内附激励文件，使用verilog编写-FPGA-based shaping filter code, which included incentives files using verilog write
FIR_lowpass
- 一个FIR低通滤波器的fpga源码，可以应用于通信调制成型滤波器参考代码-A FIR low-pass filter in the fpga source code, can be used in the communication reference code modulation shaping filter
interpolate4
- 调制信号后4倍内插的verilog代码，用于基带成型滤波器输入数据-4 times after modulation signal interpolation verilog code, used to baseband shaping filter input data
BPSK
- BPSK信号的载波调制，包含成型滤波器，上采用器以及载波生成器。(This file provides a transmitter based on BPSK signal, including shaping filter, upsampler and carrier generator.)