搜索资源列表
13-310010_FSM
- 10010序列检测，用状态机来实现，非常方便-10010 Sequence Detection using the state machine to achieve very convenient
10010
- Verilog状态机设计-10010序列检测器-Verilog state machine design-10010 Sequence Detector
seqdet
- 用verilog鉴定10010序列，用verilog鉴定10010序列-10010 sequence identification using Verilog with Verilog identification sequence 10010
10010
- verilog实现序列10010检测-verilog to achieve detection of sequence 10010
dianhua-mt8870
- 最近刚成功开发一款电话远程控制器，当听到电话里面自己录制的音频时非常高兴，觉得10010、10086那些也只是小儿科，呵呵，特把资料及自己写的代码同大家一起分享，-Recently succeeded in developing a telephone remote controller, when the hear the phone when inside their own audio recordings are very pleased to think that those are
detect_signal
- 此程序完成一个序列检测的功能，检测10010序列，适当改进，可以用于FPGA中信号检测-This process is complete a sequence of test functions, test 10010 sequence, appropriate improvements can be used for FPGA in the signal detection
Tutorial_5
- 一个序列检测器的FPGA设计实验，通过LED灯显示，基于Spartan-3e开发板-The sequence detector will look for the input series “10010.” LED’s will show how much of the series has been detected and when the entire series has been entered an additional LED will come on. Circuit input
zhuantaiji
- 简单的状态机设计，功能是检测一个5位二进制序列“10010”。考虑到序列重叠的可能，有限状态机共提供8个状态（包括初始状态IDLE）。-Simple state machine design, function is to detect a 5-bit binary sequence " 10010." Taking into account the possibility of overlapping sequences, finite state machines prov
seqdet_vm
- 在verilog下连续输入1和0，当输入为10010时输出为1，是初学者练习用的-In verilog continuous input 1 and 0, when the input is 10010 to 1 when the output is used for beginners to practice
sequence_detect
- 串行数据检测器，检测数据中是否存在10010，用FSM编写，在modelsim中仿真通过，功能上符合要求-Serial data detector detects data exists 10010, with FSM write, through simulation in modelsim functionality required
10010_xu_lie_jian_ce_qi
- 基于FPGA的序列检测器，能检测10010序列-FPGA-based sequence detector can detect a sequence 10010
state
- 实现对输入序列检测功能 1． 低电平异步复位 2． 检测序列特征为10010 3． 输出高电平，维持一个时钟周期 4． 数据序列一个时钟周期为一个数据态，时钟上升沿触发检测 -Detection of the input sequence to achieve 1. Low asynchronous reset 2. Detection sequence is characterized by 10010 3. High output, maintainin
test-series-10010
- 用于检测序列10010的程序，Verilog的状态机练习-Used to test series 10010 program, Verilog state machine practice
seqdet
- 基于verilog hdl的10010序列检测器。-10010 sequence detector based on Verilog hdl.
序列检测器
- 本例子为一个序列检测器的程序，序列为：110010010000100101００，检测的序列为10010(This example is a sequence detector procedure, the sequence is: 11001001000010010100, the detection sequence is 10010)
project_2_10010
- 检测的序列10010的一个小程序，用vivado做的(A program for detecting sequence '10010' powered by vivado 2014.4)