用verilog实现32字节8位RAM（触发器和M4K），用LPM实现RAM-32-byte by 8-bit verilog RAM (triggers and M4K), achieved by LPM RAM

Verilog硬件描述语言实现VeriRISC CPU。模块包含：8位寄存器，5位计数器，32*8 RAM，8位ALU，MUX，顺序控制器，时钟生成器。包含TB。-This code is to model a VeriRISC CPU. It incorporates several modules: 8-bit register, 5-bit counter, 32 by 8 RAM, 8-bit ALU, scalable MUX, sequence controller, and clo

32*8 RAM。Verilog实现。包含TB。-32 by 8 RAM. Testbench included.