搜索资源列表
Giga8b10b v10
- 可编程器件厂商Altera出品的8b10b编码器，用在现在通用的PCI－Express接口中，包含完全解密的源程序。-Altera programmable device manufacturers buy 8b10b encoder, now with the generic PCI-Express interface, including full decryption of the source.
Altera-AHDL语言设计的PCI总线Core
- Altera AHDL语言设计的PCI总线Core,很难得的PCI设计资料-Altera AHDL design Core PCI, the PCI is difficult to design information
Altera AHDL语言设计的PCI总线Core
- Altera AHDL语言设计的PCI总线-AHDL Altera's PCI bus design
pci
- altera pci license al tera pci license
hgb_pci_host
- 内有一PCI 主 和PCI从，PCI TARGET 都是公开代码的，是工程文件，有仿真工程，使用说明。觉得好的就推荐一下。 本PCI_HOST目前支持： 1、 对目标PCI_T进行配置； 2、 对目标进行单周期读写； 3、 可以工作在33MHZ和66MHZ 4、 支持目标跟不上时插入最长10时钟的等待。 ALTERA的PCI竟然收费的！！！软件里面调试仿真了半天，终于调通了，到了下载就突然弹出窗口说包含了有限制的IP CORE，是限制使用的
雷达数据采集FPGA
- 这是一个基于altera公司的FPGA雷达数据采集程序，可以快速的读取数据并发送到9054芯片上通过pci传递给上位机。
altera_epm1270_MAX.rar
- 一个ALTERA公司EPM1270 cpld的实验板原理图，其中有PCI接口电路，PDF格式,A ALTERA Corporation EPM1270 cpld schematic diagram of the experimental board, including PCI interface circuit, PDF format
mem32_to_pcitarget_verilog
- This design example shows how to implement interface between 32-bit pci target Altera megafunction instantiation and a 32-bit synchronous memory
AN532_PCIe_sopc_s2gx_x4
- 基于S2gx芯片的NIOS下的x4模式PCI-Express模块-NIOS based S2gx chips x4 mode under the PCI-Express Module
altera_maxII_PCI_Verilog
- Altera的MAXIICPLD模拟PCI接口的Verilog代码-Altera
opencore_crt
- 可以在Altera QuartusII下编译的Open Cores PCI桥源代码，是经过多天辛勤整理修改才完成的-Open Cores PCI bridge source code that can be compiled at Altera QuartusII. Modified under many days of hard work
sopcfpga
- 一个Altera Cyclone PCI开发板的配套样板源代码-Sample source code for An Altera Cyclone PCI development board
testbench
- altera 最新的CYCLONE IV的pci-e核的testbench，VHDL源程序。-altera latest CYCLONE IV of the pci-e core testbench, VHDL source code.
pci32tlite_oc_latest.tar
- pci32 taget core ip, The core has been designed to permit interface between a PCI Master and simple WHISBONE Slaves, and fitting into smallest FPGA (about 200 LC s in ALTERA CYCLONE II FPGA).-pci32 taget core ip, The core has been designed to p
mem64_to_pcitarget_verilog
- This design example shows possible interface between instantiation of Altera s 64-bit pci target megafunction and 64-bit synchronous memory -This design example shows possible interface between instantiation of Altera s 64-bit pci target megafunctio
pcitarget_disconnect_verilog
- This design shows how to implement a disconnect of a pci target instantiation of Altera s pci megafunction
stratix_pci_kit-v1.0
- altera PCI总线接口参考设计源代码。使用PCI编译器中的mt64兆核函数实现PCI总线接口-altera PCI bus interface reference design source code. Using the PCI Compiler mt64 trillion nuclear functions for PCI bus interface
c4gx_PCIe_gen1_x1
- 基于altera公司的cyclone4的pci-e源代码，非常好用，已经量产。-The altera Company a cyclone4 the pci-e source code, very easy to use, already in mass production.
altpcie_demo
- win7-64 altera pci express hard ip demo测试程序。-win7-64 altera pci express hard ip demo test program
PCIe_Lab(ALTERA-V5PCIe)
- 这一设计实例深入浅出，介绍怎样产生一个Qsys子系统。 您将产生一个含有以下组成的Qsys系统:在Cyclone IV GX收发器入门套件上,设计带嵌入式收发器的Gen1×1硬核IP的 PCI Express IP编译器。 -Qsys system: the Cyclone IV GX Transceiver Starter Kit, designed with embedded transceivers Gen1 × 1 hard IP PCI Express IP compiler.