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bch_encoder_decoder
- bch encoder+decoder 源代码，Flash控制器，通讯都需要用到哦
viterbi_for_bch.rar
- Viterbi based trellis decoder for (7,4) - binary BCH code,Viterbi based trellis decoder for (7,4)- binary BCH code
BCHencodeanddecode
- bch 编码和译码，用硬件语言vhdl实现-bch edcode and decoder
Full_parallel_architecture_for_turbo_decoding_of_
- A full-parallel architecture for turbo decoding, which achieves ultrahigh data rates when using product codes as error correcting codes, is proposed. This architecture is able to decode product codes using binary BCH or m-ary Reed-Solomon compo
bch-coding
- In this project, we are implementing the error detection and correction using BCH code (Bose Chaudhuri Hocquenghem). Using VHDL and targeted on FPGA for synthesis of the code. The encoder and decoder combine called as a codec.
Bch15_7
- BCH ENCODER DECODER -BCH ENCODER DECODER
syndrome
- the first step og bch code decoder part. syndrome generator
bch_dec_enc_dcd_latest.tar
- BCH译码器设计源代码，它能实现对两位错误的纠正。这是最新版本。-The BCH decoder design source code, it can achieve the two error correction. This is the latest version.
bch_dec
- BCH编解码 Features : – allows to correct up to 2 errors. – supports 16/32/64/128 bit memories (typical memory word sizes). – operates on complete memory words in a single cycle. – pure combinational logic design-The double error correcting (DE
decoder
- bch decoder 3072 3240 vhdl source code with ise software
bch3
- BCH编码、译码器，支持参数化使用，从多项式生成、编码到解码，全都有。-BCH encoder decoder
bch_dec_enc_dcd
- 关于BCH的编码器和译码器，可实现16位，32位，64位，128位的编码和译码纠错，2位纠错，Verilog实现-On the BCH encoder and decoder, can achieve 16-bit, 32-bit, 64-bit, 128-bit encoding and decoding error correction, 2-bit error correction, Verilog implementation
BCH
- BCH coder and decoder. Uses special DMA connection