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VerilogHDLchinapub
- Verilog HDL硬件描述语言 01简介.PDF 02HDL指南.PDF 03语言要素.PDF 04表达式.PDF 05门电平模型化.PDF 06用户定义原语.PDF 07数据流模型化.PDF 08行为建模.PDF 09结构建模.PDF 10其它论题.PDF 11验证.PDF 12建模实例.PDF 13语法参考.PDF-Verilog HDL Hardware Descr iption Language Introduction 01. P
robot-controller-design
- 非常全面的自平衡小车制作全套资料，包括硬件PCB，软件源代码，上位机软件代码，器件DATASHEET 等。 建模、控制算法及PD调节的取值参考： http://www.mathworks.com/matlabcentral/fileexchange/19147-nxtway-gs-self-balancing-two-wheeled-robot-controller-design 硬件及软件参考如下网站资料； http://www.circuitcellar.c
Switch
- 模拟了一个100个端口的交换机，同时模拟了100台PC。PC机初始了MAC和所连的交换机端口，且随机的产生一条数据帧，发向其他PC。 学习二层交换机的存储转发的基本原理。 -Simulation of a 100-port switch, while modeling the 100 PC. PC, MAC and the initial of the connected switch port, and generate a random data frame, sent to the
verilog_intr
- Verilog Overview n Basic Structure of a Verilog Model n Components of a Verilog Module – Ports – Data Types – Assigning Values and Numbers – Operators – Behavioral Modeling • Continuous Assignments • Procedural Blocks –
DatAnalysisSA
- analysts today are finding myriad uses for categorical data methods. In this book we introduce these methods and the theory behind them. Statistical methods for categorical responses were late in gaining the level of sophistication achieved early in
papaya_0.97.20031122.orig.tar
- Recent advances in wireless sensor networks have led to many new protocols specifically designed for sensor net- works where energy awareness is an essential consideration. Most of the attention, however, has been given to the routing protocol
routing_survey
- Recent advances in wireless sensor networks have led to many new protocols specifically designed for sensor networks where energy awareness is an essential consideration. Most of the attention, however, has been given to the routing protocols sin
10.1.1.11.9103
- This paper proposes an adaptive threshold estimation method for image denoising in the wavelet domain based on the generalized Guassian distribution (GGD) modeling of subband coefficients. The proposed method called NormalShrink is computat
AlgorithmsandDataStructures
- While many computer science textbooks are confined to teaching programming code and languages, Algorithms and Data Structures: The Science of Computing takes a step back to introduce and explore algorithms -- the content of the code. Focusing on thre
std_logic_1164
- 这个包定义了vhdl标准,为设计者在使用数据类型时建立用于vhdl的互连模型。-This packages defines a standard for designers to use in describing the interconnection data types used in vhdl modeling.
advances
- Advances in object oriented data modeling cooperative information systems
Multi-sensor-technology
- 多传感器技术及其应用。传感器领域宝典书籍，国防基金资助翻译的德国资料。介绍多参数系统从建模到电路接口到软件实现的理论及其应用。应用及其广泛：生物，汽车，化学，医疗，农业，智能，通信等等，未来属于多传感器系统。 -Multi-sensor technology and its applications. Sensor field Collection of books, translation of the German Defense Fund data. Modeling of multi
DimensionalPModelingP(w6)
- data warehouse about dimensional modeling
Example-4-16
- 串并转换建模 数据流串并转换的实现方法多种多样，根据数据的排序和数量的要求，可以选用移位寄存器、RAM等来实现。对于数据量比较小的设计来说，可以使用移位寄存器完成串并转换；对于排列顺序有规定的串并转换，可以用case语句判断实现；对于复杂的串并转换，还可以用状态机实现-Modeling serial data stream and convert the realization of string and convert many ways, sort and quantity of the
verilog-Streamline-tutorial
- Verilog HDL 语言具有下述描述能力：设计的行为特性、设计的数据流特性、设计的结构 组成以及包含响应监控和设计验证方面的时延和波形产生机制。所有这些都使用同一种建模 语言。此外， Verilog HDL语言提供了编程语言接口，通过该接口可以在模拟、验证期间从设 计外部访问设计，包括模拟的具体控制和运行。-Has the following descr iption of Verilog HDL language ability: the behavior of the des
Interactive-state-machine
- 交互状态机建模，交互状态机能够使用通过公共寄存器通信的独立的a l w a y s语句进行描述。 示的两个交互进程的状态图， T X是一个发送器， M P是一个微处理器。如果进程T X不忙，进 程M P将要发送的数据放置在数据总线上，然后向进程T X发送信号L o a d T X，通知其装载数据 并开始发送数据。进程T X在数据传送期间设置T X B u s y表明其处于忙状态，不能从进程M P接 收任何进一步的数据。-Interactive state machine mode
Experiment10
- FPGA低级建模试验二串口定时发送数据，通过板级调-FPGA test two low-level modeling time to send serial data transfer through the board
fifo_module
- 基于vhdl的FIFO建模，主要是用于输入输出数据缓存-Vhdl-based FIFO modeling is mainly used for input and output data cache
AD-data-collection
- 微小倾转动力飞行器实验建模系统设计与实现 串口数据采集程序-The slight tilting vehicle in experimental modeling system design and serial data acquisition program
VHDL-Code-For-Half-Adder-By-Data-Flow-Modeling.zi
- VHDL Code For Half Adder By Data Flow Modeling