搜索资源列表
7seg_led
- 使用xilinx公司的FPGA实现了七段码的定时器时钟程序-use of the Xilinx FPGA in paragraph 107 of the Code timer clock procedures
top
- FPGA程序的top.v文件，主要实现DDS信号发生器功能，通过定时器，可简单实现输出幅值无极跳变-FPGA procedures top.v documents, the main function of DDS signal generator, through the timer can be simple to achieve the output amplitude wuji hopping
DigitalClock
- 基于FPGA的数字电子钟设计，系统总程序由分频模块、“时分秒”计数器模块、数据选择模块、报时模块、动态扫描显示和译码模块组成。得到一个将“时”、“分”、“秒”显示于人的视觉器官的计时装置。它的计时周期为24小时，显示满刻度为23时59分59秒，另外有校时、校分和整点报时功能，并通过数码管驱动电路显示计时结果。-FPGA-based design of digital electronic clock, the system program by the total frequency modul
MyPWM
- 基于FPGA ALTERA EP2C5Q8208C8，自制PWM控制器，配合上位机定时器-based on FPGA ALTERA EP2C5Q，PWM controller,with MCU TIMER
pwm_timer
- PWM和Timer的FPGA实现，文档代码齐全。-PWM and Timer for FPGA implementation, documentation, code complete.
time_three
- 基于sopc的三个定时器的三种应用，希望可以帮到学习FPGA的人，谢谢！-The three timer-based sopc three applications, the desire to help people learn FPGA, thank you!
RS232_FIR
- Quartus II was a development tool of CPLD / FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: a
program
- 1/100s计时器的FPGA实现，本设计的计时器能实现显示最长计时时间为1分59.99秒，且精度大于1/100s，计时器能显示1/100s的时间.-1/100s timer FPGA, the design of the timer to achieve the longest time show time of 1 minutes, 59.99 seconds, and the precision is greater than 1/100s, 1/100s timer can display
Reflex
- This simple program tests the reflex of a person. It will randomly start a timer and after some seconds the person will be told to press a certain button. The CPLD or FPGA will know with a resolution of 1mS the time elapsed time between the command a
basketball24
- 基于FPGA的篮球24秒计时器，开发环境为MAXPLUS-24 second timer in the FPGA-based basketball,Development environment for MAXPLUS
miaobiao
- 它具有计时功能。此秒表有两个按键（reset， start）按下reset键后，秒表清零，按下start键后，开始计时，再次按下start键后， 暂停计时，秒表显示内容闪烁。 用FPGA开发板上的两个七段数码管显示时间（以秒为单位），计时由0 到 59 循环。-It has a timer function. This stopwatch has two buttons (reset, start) reset button is pressed, the stopwatch is clear
nios-II
- NiosII范例，包括了DMA控制，串口通信，定时器中断，以及NIOS的部分范例，对于FPGA内核的开发很有帮助。-NiosII example, including the DMA control, serial communication, timer interrupt, as well as some examples of NIOS, development will be helpful for the FPGA core.
nios_ii-irq
- ALTERA FPGA 构建nios ii CPU ——中断法定时器 本例子教你学会FPGA NIOS中断，熟悉中断，逐步深入。-ALTERA FPGA build nios ii CPU- to interrupt method timer this example teach you to learn to FPGA NIOS interrupt, familiar interrupt gradually deepened.
timer
- 基于FPGA nios II 的软核处理器 定时器的应用程序-Based on FPGA nios II soft-core processor timer application
timer
- 基于fpga的定时器，嵌入式开发，调试通过-Fpga-based timers, embedded development, debugging through. .
TIMER
- FPGA verilog 秒表TIMER功能-FPGA verilog THIS IS A TIMER
clock-with-alarm-and-timer
- FPGA example, the timer buzzer. Can learn the FPGA involved in the grammar!-FPGA example, the timer buzzer. Can learn the FPGA involved in the grammar!
FPGA-8253
- 本文就基于 FPGA微机与接口实验平台设计的问题，首先讲述了 核心板的设计。在 FPGA基础上，以可编程计数器 / 定时器 8253 和可编程并行控制器 8255为例，并介绍了 8255 和 8253 接口芯片，用 VHDL语言设计了8255 和 8253 的功能，最后在 ModelSim SE开发软件上实现了编译、调试、-In this paper, based on FPGA computer and interface experimental platform design issues
至简设计法--篮球倒计时
- 24秒计时器的FPGA实现，分三个模块并内分别附上VHDL程序(24-second timer FPGA implementation)
counter
- 基于fpga的倒计时器。 可实现6位数的倒计时，通过按键设置初始值，倒计时结束提醒等功能(An inverted timer based on FPGA)