搜索资源列表
USB 2.0 IP Core
- USB20的IP CORE,可以直接用在SOPC下，自动完成全部的枚举，只需修改枚举参数即可！-USB20 IP CORE, can be directly used in SOPC, automatically complete the enumeration. only a modification of enumerated parameters can be!
PS2-IP-CORE-VHDL
- 一个PS2 IP CORE(VHDL) for FPGA
USB 1.1 IP-CORE和设计范例 VHDL源代码
- USB 1.1 IP-CORE和设计范例 VHDL源代码-Sample program for USB1.1 IP core design, VHDL source code
IP core
- VHDL ip core的设计，软核的设计方法-VHDL core of the design, soft-core design
quartus 9.0 中FFT IP核的使用方法
- quartus 9.0 中FFT IP核的使用方法附带工程文件和用signaltapII抓到的波形,quartus 9.0 in FFT IP core attached to the use of engineering documents and the use of captured waveform signaltapII
USB.rar
- 用VHDL实现的USB IP核，大家可以参考下,Use VHDL to achieve USB IP core, we can refer to the following
usb11.rar
- 基于verilog HDL的一个USB 1.1的IP 核，内有详细文档说明。,Verilog HDL based on a USB 1.1 of the IP core, which has detailed documentation.
USB2.0IP.rar
- 完整的用VERILOG语言开发的USB2.0 IP核源代码,包括文档,Complete Verilog language developed by USB2.0 IP core source code, including documentation
Altera_8051_IPcore_v1.2.rar
- Alera 的8051 IP core的示例文件5个,Alera the 8051 IP core of the sample file 5
can.rar
- can IP CORE .VERY GOOD AS A STUDY FILE,can IP CORE. VERY GOOD AS A STUDY FILE
fft_verilog.rar
- FFT IP core 源码 状态控制机,FFT IP core
Quartus_fft_ip_core.rar
- Quartus中fft ip core的使用(modelsim 仿真FFT ip core 结合QUARTUS II 联合调试),Fft ip core in Quartus use (modelsim simulation FFT ip core integration QUARTUS II Joint Commissioning)
VERILOG-USB2.0IP-core
- 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-VERILOG language with a complete development of USB2.0 IP core source code, including files, simulation files
uartvhdl
- VHDL语言实现的UART IP核，比较实用-VHDL language to achieve the UART IP core, more practical
ethernet
- 以太网MAC层IP核设计Veriolg代码，包括TESTBECH平台和设计文档-Ethernet MAC layer IP core design Veriolg code, including TESTBECH platform and design documents
I2C_IP_core
- I2C IP CORE 及开发文档, 网上搜集-I2C IP CORE and the development of documentation, on-line collection of
ARMcore
- 基于FPGA的ARM IP核！该软核VHDL源码全部开放-FPGA-based ARM IP core! The soft core VHDL source code are all open
15-IP-core
- 15个免费的IP核 IP核源代码 -15 IP cores
ethernet10-100M-IP-core
- 以太网10-100M IP核Verilog源码，可综合-Ethernet 10-100M IP core Verilog source code can be integrated
vhdl-fft-core
- FFT ip core，fft信号处理模块， VHDL语言编写-FFT ip core