搜索资源列表
fpga-fir
- xlinx fpga 利用verilog语言实现fir滤波器功能，完整ise工程文件直接可以使用-xlinx fpga verilog language the fir filter function, complete ise project file can be used directly
I2C-bus-based-on-FPGA
- 基于FPGA设计I2C总线，使用Verilog语言，ISE环境，含有仿真结果-I2C bus based on FPGA design using Verilog language, ISE environment containing simulation results
ram2114
- 本程序是利用ise平台设计出的ram2114的Verilog源代码，通过上机运行检测。-This procedure is to use the platform to design a ram2114 ise of Verilog source code, the test is run through the machine.
spi
- spi协议 用verilog 编写 可以在xilinx fpga板子上 ise软件-spi protocol written in verilog in xilinx fpga board ise software
my_bayer2rgb
- 摄像头Bayer 转rgb信号 用verilog 编写 在xilinx fpga 软件下 ise 综合 编译-Bayer turn the camera rgb signal in xilinx fpga verilog prepared under ise integrated compiler software
I2C
- iic协议 用verilog hdl语言，可以在xilinx ise软件 编译 综合-iic agreement verilog hdl language can be compiled in xilinx ise software integrated
juanji_3_3
- 自己写的3*3的高斯卷积模板，用Verilog在ISE上写的-Write your own 3x3 Gaussian convolution mask, using Verilog write on the ISE
a
- 用verilog实现除法器，调用了ip核，不仅有源代码，还有测试程序的时序编写-verilog ise divider
multi_cpu
- 用xilinx ISE 14.3开发的多周期CPU系统，开发语言为verilog HDL.仿真调试与实际测试均已通过-Using xilinx ISE 14.3 development of multi-cycle CPU system, development language for verilog HDL. Simulation debugging and practical tests have passed
Watch_Game_0729
- 基于xilinx virtex5的猜数游戏+LCD显示设计，包含完整的ISE工程文件，代码全部用verilog编写，有说明文档。-Based on xilinx virtex5， the guessing game plus LCD display design, including complete ISE project file, all code written in verilog, documents.
StopWatch
- This a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.-This is a simple verilog code for stopwatch undre xlinx ISE webpack based for NEXYS3 board.
18B20
- verilog 写的18b20温度采集程序，并通过串品模块送出-verilog 18b20 uart ise
Experiment04
- 浮点数的除法器的Verilog 源代码，使用Quartus II开发环境编写，塞琳思的ISE可能打不开-floating-divider s Verilog codes,can be opened by Quartus and not by ISE
paobiao
- ISE仿真平台下建立的用verilog语言实现的简易数字跑表工程-Simple digital stopwatch works with verilog language of the establishment of the ISE simulation platform
gate4
- 运用verilog 语言编程，实现4输入逻辑门设计，利用ISE软件仿真，把程序下载到BASY2开发板上运行实现。-BASY2 engineered for ISE
16QAM
- 使用verilog编写的16QAM调制解调代码，可用于quartus和ISE，因为不包含FIR，只能用于仿真，不能用于实际通信-Verilog prepared using 16QAM modulation and demodulation code can be used quartus and ISE, because they do not contain FIR, only for simulation and not for actual communication
inv_matrix
- 矩阵求逆模块硬件实现,用verilog语言，基于ISE开发环境-implement of inverse matrix
cordic
- cordic代码 verilog语言 产生三角波 适用在ISE上面-cordic code verilog language triangular wave generated above apply at ISE
turbo_encode
- turbo码的编码程序,verilog HDL,在ISE环境中-turbo code encoding process
Lab3_mux24a
- 4位2选1多路选择器的设计与实现。nexy3开发板。本实验中用Verilog语句来描述。-Xilinx ISE 12.3.nexy3.