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等精度频率计
- 使用vhdl语言写的fpga的应用程序，使献策内容为等精度频率计-use of the VHDL language they simply write the application procedures so that such ideas as to accuracy Cymometer
数字频率计实验报告
- 课程设计要求设计并用FPGA实现一个数字频率计，具体设计要求如下： 测量频率范围： 10Hz～100KHz 精度： ΔF / F ≤ ±2 % 系统外部时钟： 1024Hz 测量波形： 方波 Vp-p ＝ 3～5 V 硬件设备：Altera Flex10K10 五位数码管 LED发光二极管 编程语言：Verilog HDL / VHDL-curriculum design and FPGA design to achieve a digital frequency meter,
dengjingdu.rar
- 根据第三届（1997年）全国大学生电子设计竞赛题目：简易数字频率计，完全用FPGA芯片做的一个等精度数字频率计。,According to the third (1997) National Undergraduate Electronic Design Contest Topic: simple digital frequency meter, complete with a FPGA chip, such as doing precision digital frequency meter.
基于FPGA的自适应数字频率计
- 基于FPGA的自适应数字频率计，测量范围1Hz-99.9MHz,FPGA-based adaptive digital frequency meter, measuring range 1Hz-99.9MHz
97B
- 这是电子设计大赛的97年b题简易数字频率计的fpga一种做法。-This is Electronic Design Competition 1997 b problem simple digital frequency meter fpga practice.
pinglvji
- 做的等精度频率计，采用等精度测量原理，即利用双计数器“相关计数”和“硬件同步分频”实现高低频率的等精度的测量。用FPGA实现频率测量、周期测量、时间间隔测量、相位测量及脉冲宽度的测量。所有的测量功能都由VHDL语言编程实现。-I do other precision frequency meter, use and other precision measuring principle, namely the use of dual-counter " related counts&qu
FPGA--cepin
- 几个关于用vhdl 语言，编写测频，频率计程序的论文，希望对初学者有用！-Vhdl on the use of several languages, write frequency measurement, frequency meter program of papers, I hope useful for beginners!
fangzhen
- vhdl代码： 采用等精度测频原理的频率计程序与仿真！初学fpga者可以参考参考！！比较简单-VHDL code: Using the principle of frequency measurement accuracy, such as the frequency of procedures and simulation! FPGA beginner who can refer to reference! ! Relatively simple
plj
- 数字频率计是一种用来测试周期性变化信号工作频率的装置。其原理是在规定的单位时间（闸门时间）内，记录输入的脉冲的个数。我们可以通过改变记录脉冲的闸门时间来切换测频量程。本文利用EDA技术中的Max+plusⅡ作为开发工具,设计了基于FPGA的8位十进制频率计,并下载到在系统可编程实验板的EPF10K20TC144-4器件中测试实现了其功能。-Digital frequency meter is a kind of cyclical changes in the signal used to tes
FPGA-baseddesignofdigitalrequencymeter
- 基于FPGA数字频率计的实现，文中有所有的源代码，仅供参考。-FPGA-based realization of the digital frequency meter, text in all the source code, for reference purposes only.
FPGA
- 基于FPGA的数字频率计的设计11利用VHDL 硬件描述语言设计,并在EDA(电子设计自动化) 工具的帮助下,用大规模可编程逻辑器件(FPGA/ CPLD) 实现数字频率计的设计原理及相关程序-FPGA-based design of digital frequency meter 11, the use of VHDL hardware descr iption language design, and EDA (electronic design automation) tools with
E_8051_FTEST_K4X4_new
- 是带５１单片机核的等精度频率计的ＦＰＧＡ设计的部分。用ＶＨＤＬ编的，也有ＶＥＲＩＬＯＧ的。-51 is a single chip with precision, such as the nucleus of the frequency of some of FPGA design. VHDL for use as well as the VERILOG.
dds_vhdl
- fpga VHDL语言，控制DDS产生频率可变的正弦波信号扫频-FPGA VHDL DDS
main
- 交通信号灯 原代码 西安交通大学 电信学院 FPGA设计课下作业-Traffic lights of the original source, Xi' an Jiaotong University School of FPGA design course telecommunication operating under the
LCDfcout
- FPGA实现LCD显示的频率计，芯片为cyclone-FPGA realization of the frequency meter LCD display chip for the cycloneII
vhdl
- 基于FPGA的等精度频率计 频率测试功能：测量范围1Hz～20MHz。测频精度：测频全域相对误差恒为万分之一基于FPGA的等精度频率计-based on FPGA precision frequency meter
FPGA-VHDL-dengjingduc
- 本文介绍了基于VHDL语言的十进制等精度频率计的设计，采用VHDL 语言，运用自顶向下的设计思想，将系统按功能逐层分割的层次化设计方法，使用Quartus8.0开发环境，实现了频率计的设计。 -This article describes the decimal-based VHDL, and other precision frequency meter design, using VHDL language, the use of top-down design, the system
Frequency-counter
- 基于FPGA的频率计设计。通过FPGA运用、 HDL编程，利用FPGA(现场可编程门阵列)芯片设计了一个8位数字式等精度频率计，该频率计的测量范围为0-100MHZ，利用QUARTUS II集成开发环境进行编辑、综合、波形仿真，并下载到CPLD器件中，经实际电路测试，仿真和实验结果表明，该频率计有较高的实用性和可靠性。-Frequency counter FPGA-based design. By using FPGA, VHDL programming, the use of FPGA (fi
FMT
- 基于vhdl设计的数字频率计，后面还加了个与fpga通信的模块(Digital frequency meter based on VHDL design, and later added a module to communicate with FPGA)
frenq2
- 数字硬件频率计 带有频率测量和占空比测量功能(Digital hardware frequency meter Frequency measurement and duty ratio measurement function)