搜索资源列表
Verilog_HDl_Code
- 《精通Verilog HDL语言编程》中的Verilog实例源码-Verilog HDL Code
ALUALUcontrol
- 实现32位的ALU，使其能够支持基本的指令。用Verilog HDL语言或VHDL语言来编写，实现ALU及ALU控制器。 -To achieve 32-bit ALU, so that it can support the basic directives. With the Verilog HDL language or VHDL language to write, implement ALU and the ALU controller.
111
- Verilog语言编写的循环彩灯控制器 这个程序我已经在Actel板上烧过了，没问题。如果还有什么问题应该是你的板不同或者工具不同，我是在libero_8.5上做的 -VeriloG HDL IS VEVRY USEFUL
Ringcounter
- ringcounter verilog HDL example code
verilog_code
- 《Verilog HDL程序设计教程》程序源码(王金明)-" Verilog HDL Programming Tutorial" program source code (Wang Jinming)
paobiao
- 基于Verilog HDL的完整数字跑表工程，在试验机台上运行验证通过了的。 用8位7段数码管分别显示微妙，秒，分。 有开始，暂停，复位功能。 学习VerilogHDL的经典例子，添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube sho
example
- 自己编写的经过QuartusII验证的Verilog HDL程序，可以实现常见功能-After QuartusII their written procedures for verification of the Verilog HDL, can achieve common features
verilog_seg7
- 买的Altra公司的一款Max II EPM1270T144的电路板，其中的一个用Verilog HDL 编写的驱动数码管的程序，完全可用。-Altra Inc. bought a Max II EPM1270T144 circuit board, one written in Verilog HDL using the digital controls process-driven, fully available.
szdyb
- 基于Verilog HDL的数字电压表的程序-Verilog HDL-based procedures for the digital voltmeter
countor
- This code for countor . it is design in verilog HDL.
82_Examples_for_VHDL_and_Verilog_code
- 包括VHDL、verilog在内的各种设计实例，是学习硬件描述语言的帮手。共有82个实验例子，涉及各种语法规则。-82 VHDL, verilog test case, involving a variety of grammatical rules. which is you learn the HDL language helper.
cardTEL
- 基于verilog-hdl的卡式电话电路，编译环境quartusII72，经下载仿真通过。-Verilog-hdl cassette based on telephone circuits, build environment quartusII72, has been downloaded by simulation.
synchronousSerialDataTransfer
- 周立功教科书上的同步串行传输verilog.hdl程序源码及工程文件，是用quartus ||综合过的了-synchronous serial data transfer
rs232
- 异步串行传输的verilog hdl 功能文件以及测试文件-The verilog hdl source and the testbench of asynchronous serial transmission
HA
- Verilog HDL for Half Adder, Full Subtractor, Half Subtractor and 2x4 decoder.
controller
- PI controller and its source code
digital_clock
- verilog hdl digital clk
BULKFPGA
- 用quartus2编写的,Verilog HDL,测试BULK和FPGA通讯的程序-With quartus2 written, Verilog HDL, testing, and FPGA communication procedures BULK
61EDA_D888
- 基于Verilog HDL出租车计费系统的研制-Based on Verilog HDL Taxi Accounting System
clock
- 用Verilog HDL编写的电子钟,实现一些简单功能,包括计时,调时-Written in Verilog HDL using electronic clock to achieve some simple functions, including timing, tone, when