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uart
- 本例程是用verilog硬件描述语言在quaryusII环境下开发的串口通信模块，分为发送模块，接受模块和波特率产生模块。-This routine is verilog hardware descr iption language development environment under quartus II serial communication module, divided into send module, receive module and baud rate generato
dac_900
- DAC900芯片驱动的Verilog语言描述，亲测可用。另外的是FIR滤波代码和DDS波形发生器的代码。既可单独使用，也可以整合在一起。-DAC900 chips driven Verilog language descr iption, pro-test available. Another is the FIR filter code and DDS waveform generator code. Either used alone or can be integrated.
ClockGenerator
- Verilog code for a programmable clock generator
boxingfashengqi
- 波形发生器的源代码，有正弦波，三角波，锯齿波，方波。modelsim仿真，包含testbench仿真代码，testbench用的verilog编写，波形发生器源代码用的VHDL编写。-Waveform generator source code, sine, triangle, sawtooth, square wave. modelsim simulation, testbench simulation code contains, verilog write testbench use, w
dds_generater
- 波形发生器，可以生成正弦波、三角波、方波、锯齿波；可以选择输出频率和幅度，基于DDS设计，verilog和QuartusII开发-Waveform generator can generate sine, triangle, square wave, sawtooth wave you can the output frequency and amplitude, DDS-based design, verilog and development QuartusII
CCD_frequency_generator
- CCD工业相机六路频率发生器，VHDL语言实现，非Verilog HDL-CCD industrial camera image capture six-way frequency generator, VHDL language, non Verilog HDL.
DDS
- 基于FPGA，Verilog语言编写的DDS信号发生器，可生成方波、正玄波，三角波。-Based FPGA, Verilog language DDS signal generator that generates a square wave, sine wave, triangle wave.
singnt
- 基于verilog的正弦发生器,可以产生正弦信号-Based verilog sine generator，Can produce a sinusoidal signal
dds
- 这是一个用Verilog语言实现的一个数字信号产生器算法-This is a use Verilog language implementation of a digital signal generator is presented
FPGA_phase_lock_demodulation
- FPGA 用Verilog语言实现数字锁相解调系统，包含了正交的DDS函数发生器和相应的AD驱动-FPGA digital demodulation system in Verilog lock, comprising a DDS orthogonal function generator and driving the corresponding AD
dds_synthesizer
- Verilog编写的基于DDS的信号发生器，频率可变。(Verilog prepared by the DDS-based signal generator, the frequency variable.)
ahb_system_generator_latest.tar
- amba ahb master generator by using verilog