搜索资源列表
Sparc_leon_VHDL
- 一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码，但不能保证版图设计ASIC成功 -the Sparc processor (fitted with the United States of the European Space Agency R_tems Embedded operating system) VHDL source code, but it can not guarantee success ASIC Layout
VHDL_100Examples
- 北京里工大学ASIC设计研究所的100个 VHDL程序设计例子-Beijing University Institute of ASIC design hundred examples of VHDL Design
2006620165231JoY5pZfmvSPHMBQVNp3V
- vhdl语言例程100个，专用集成电路（ASIC）设计-vhdl language routines 100, application specific integrated circuit (ASIC) design
USB2.0IP(RTL)
- USB2.0 IP核,ASIC,FPGA可用,Verilog HDL源代码-USB2.0 IP,Verilog HDL
fpgashixiantongxin
- 提出了一种利用FPGA技术解决ARINC429通信的实现方案,该方案不仅使国内的ARINC429通信设备摆脱了对国外ASIC电路的依赖,还降低了设备成本,并且克服了国外ASIC电路的不足,实现了任意长度数据帧的群收和*功能,具有较好的应用前景。利用该方案研制的ARINC429数据通信卡,已成功应用于空空导弹测控设备中。 -A use of FPGA technology to solve ARINC429 Communication program, which not only make
adaptive_lms_equalizer_latest.tar
- In communication systems channel poses an important role. channels can convolve many different kind of distortions to our information. In perticular wireless channels multipath distortion is sevear. and more sevear is such distortion is random.
hdlc-code
- 用硬件描述语言实现HDLC通道的功能,取代HDLC专用芯片-Hardware descr iption language used to achieve the functions of HDLC channel to replace the HDLC ASIC
BP062-BU-01000-r0p0-00rel0[1][1].tar
- AXI协议检查器，由ARM公司开发对于想开发AXI master和slave模型的ASIC设计人员非常有用！-AXI protocol checker, developed by ARM to develop for the AXI master and slave model is very useful ASIC designers!
ASIC_Design_Flow_Tutorial_with_synopsys
- Tutorial from VCS to IC Compiler for ASIC design using synopsys tool. .
Essential-Vhdl
- A brief introduction to design with VHDL for ASIC design.
dqpsk_demodulator_f_pa
- FSK QPSK DQPSK 等verilog 源码 及asic实现-FSK QPSK DQPSK and asic implementation such as verilog source
MAC_Transceiver
- MAC(以太网媒体访问控制)是以太网IEEE 802.3协议规定的数据链路层的一部分,使用FPGA替代ASIC,实现以太网MAC功能非常实用。能够实现硬件系统多路多端口的以太网接入,并在自行开发需要以太网接入的嵌入式处理器设计中得到应用。具体探讨以太网MAC的功能定义,使用FPGA实现以太网MAC的方法,对以太网的相关应用设计具有指导作用。 -MAC (Ethernet Media Access Control) is a protocol under the IEEE 802.3 Ethe
memtest
- 在数字系统中，一般存在多个芯片，利用不同的特点用于实现不同的功能，一般都包含CPU,FPGA,AD,DA,memory，ASSP（专用标准模块）,ASIC等。CPU用于进行智能控制，FPGA进行硬件算法处理和多设备接口，AD进行模数转换，DA进行数模转换，memory存储临时数据。因此，FPGA如何与其他芯片进行通讯是重要的设计内容。数据输入，数据输出，双向通讯，指令传递，地址管理，不同时钟的异步通讯问题等等都需要处理。最基本的MEMORY如SRAM(128KX8bbit静态存储器628128)
AsicVhdlBasicLab_Vhdl
- Asic Vhdl Basic Ans Lab_Vhdl Examples_microprocessor (VHDL)desingn
ASIC.and.FPGA.Verification.A.Guide.to.Component.Mo
- ASIC的FPGA模型设计，VHDL版 英文原版书籍-ASIC.and.FPGA.Verification.A.Guide.to.Component.Modeling.Morgan.Kaufmann
ASIC_VHDL_FPGA_design_lectureNotes
- 这是美国普渡大学（Purdue University West Lafayette)ASIC design 的课件完整版！带事例和讲解的非常好的VHDL学习材料！含有vhdl 基础知识，设计步骤，UART, RTL,Test Bench 以及测试和调试，DEBUG等各种VHDL设计者必学知识！-This is Purdue University (USA) ECE 337 ASIC design class lecture notes! very classic! The content inc
PIANo
- （1）下载“KX232_PIANO_C5T”文件夹中的sof文件。 (2) 接上串行通信线，与PC机通信。 （3）在“FOR_PC_FILE”文件夹中，双击打开上位机软件“SEND”,按键盘上的“1、2、3.。。”即可弹琴。SEND窗口即显示对应的ASIC码。-(1) Download " KX232_PIANO_C5T" folder in the sof file. (2) connected to the serial communication lines, a
44317447-Vhdl-Sim-Syn
- This document is meant to be an introduction to VHDL both as a simulation language and an input language for automatic logic synthesis. It is based on material originally prepared for the ASIC Design Laboratory taught at the University of Twente
UART-VHDL-Example-Code-for-an-FPGA-or-ASIC-from-n
- UART code using VHDL for FPGA or ASIC
avs_aes_latest
- This is source code for something very important that is AVS AES standard hardware code for implementation both ASIC and FPGA