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verilog实例 [43项]
- 嵌入式可编程器件CPLD的典型实例 压缩包，共计43个源码文件。 使用ALTERA的 Muxplus 软件即可编辑仿真 相关软件可在教育网ftp下载[天网查询，有很多站点提供]-Embedded Programmable CPLD in a typical example of compressed, for a total of 43 source document. Altera Muxplus use the software can edit simulation software av
能综合的YCrCb2RGB模块（verilog)_采用3级流水线
- 能综合的YCrCb2RGB模块（verilog)_采用3级流水线,用fpga做小数运算，还有就是流水线技术 -can YCrCb2RGB integrated module (Verilog) _ used three lines, they simply do with fractional arithmetic, there is pipelining technology
CAN协议控制器的Verilog实现
- 基于FPGA的CAN总线控制器，VERILOGHDL源代码，Q2仿真实现。可用。-FPGA-based CAN Bus Controller, VERILOGHDL source code, Q2 Simulation. Available.
THS5651是一款高速DA转换器
- THS5651是一款高速DA转换器，最高转换频率可到达100MBPS，该程序利用VHDL语言对THS5651进行控制,THS5651 is a high-speed DA converter, the maximum conversion frequency can be arrived at 100MBPS, the use of VHDL language in the process control of the THS5651
iic 用verilog语言写的FPGA iic驱动程序
- 用verilog语言写的FPGA iic驱动程序，实现对存储器的读写，有需要的可以下载看看哦！-Language used to write verilog FPGA iic driver to achieve the memory read and write, there is a need can be downloaded to see Oh!
Verilog.Verilog编写的出租车计价器程序
- Verilog编写的出租车计价器程序，可以设置按路程计价，按等待时间计价。非常方便，界面良好,Verilog program, prepared a taxi meter can be set according to distance pricing, valuation by waiting time. Very convenient, good interface
Sdram_Control_4Port.Verilog写的sdram的控制器
- 已经验证可用。此代码为Verilog写的sdram的控制器，可以由用户的使用而加载到自己的项目中自行开发。,Have verified that is available. This Verilog code written sdram controller, can be loaded into the user' s use of their own self-developed projects.
ledcount60.verilog语言书写 用数码管显示
- verilog语言书写 用数码管显示，60位的计数器，加上分频模块可以实现时钟功能,verilog language digital display, 60-bit counter, together with the sub-frequency clock function modules can be achieved
can-bus
- CAN总线控制器的VERILOG工程文件,很实用，工程是ISE可以打开，也可以只使用工程里面的代码-can bus project with VERILOG
DAC-use-verilog
- 用verilog写的TLV5620芯片的DAC转换代码，核心文件dac.v，能进行实现，不仅仅是行为级描述-Written with verilog conversion code TLV5620 DAC chip, the core file dac.v, can be achieved, not just behavioral descr iption
graph-acceleration-verilog
- 2D图形加速，里面有串口模块。可以综合，为本人毕业设计。-2D graphics acceleration, which has the serial port module. Can be integrated, as my graduation project.
verilog-mac
- 这是一个以太网的mac程序，verilog写的，可方正 可实现-this is a mac implementation using verilog，you can emulate it or implement it directly
Verilog code about a VGA based ball and gun game
- This code can be performed directly on the SPARTAN-3A FPGA board as long as a VGA port is connected to this board. After initialization, a ball and gun will appear on the screen and you can control them and playing the game by using the button from t
Verilog黄金指南中文版
- FPGA教程，其中大量讲解了一些例程，可以很好的初步学习FPGA，好入门(FPGA tutorial, which explains a lot of routines, can be a good preliminary study FPGA, a good entry)
Verilog的135个经典设计实例
- 编程基础包括一些实用例子，有中文注释，可以直接阅读(Programming basis, including some practical examples, there are Chinese notes, you can read directly)
Verilog HDL使用中该注意的问题及一些模块代码
- cpu仿真，提供vivado上的cpu仿真生成文件(cpu simulated,but no one can get 20 words in this short file how can I do? just tell you the simulated file and vivado system is 2015)
Alter官方FFT程序(使用Verilog编写)
- 其主要使用verilog编写fft程序主体，之后通过quartus和matlab实现对fft程序的测试，可以很好做到自动化验证(The main use of verilog prepared fft main program, and then achieved by quartus and matlab fft program testing, you can do a good job of automated verification)
eetop.cn_利用FPGA实现浮点运算的verilog代码
- 计算机里整数和小数形式就是按普通格式进行存储，例如1024、3.1415926等等，这个没什么特点，但是这样的数精度不高，表达也不够全面，为了能够有一种数的通用表示法，就发明了浮点数。 浮点数的表示形式有点像科学计数法（*.*****×10^***），它的表示形式是0.*****×10^***，在计算机中的形式为 .***** e ±***），其中前面的星号代表定点小数，也就是整数部分为0的纯小数，后面的指数部分是定点整数。利用这样的形式就能表示出任意一个整数和小数，例如1024就能表示成0.
CAN总线，I2C，USB等的FPGA实现源码
- 控制器局域网总线协议的Verilog代码(The Verilog code of the CAN bus protocol)
fpga_can_read_write
- FPGA实现can通讯 已经调试成功 mcp1050(FPGA realizes can communication)