搜索资源列表
Walsh
- 利用ISE编写的产生WALSH码的verilog程序,简单易懂,稍稍修改就可以产生出自己想的8 16 32 64位的WALSH码-Prepared using ISE verilog code generated WALSH procedures, easy to understand, a little modification can generate their own like the 8,16,32,64-bit code WALSH. .
counter_3
- 三种计数器的verilog实现,二进制计数器,格雷码计数器,约翰逊计数器.初学硬件描述语言可参考。-Three kinds of counter verilog implementation of a binary counter, gray code counter, Johnson counter beginner hardware descr iption language can refer to
bridge
- FPGA和A/D转换芯片ad7862的IP,可实现4路数据的采样和读取。 用verilog实现的-FPGA and the A/D conversion chip ad7862' s IP, can achieve 4-way data sampling and reading. Achieved with verilog
recuart_50m
- 本代码功能为实现接收PC发送的串口数据功能 程序通过quartusII 8.1编译,使用verilog语言编写。 可在彬杰科技*BJTECH公司基于altera epm240的开发板上验证。 (开发板网址http://item.taobao.com/auction/item_detail-0db1-69fe7069aa3ba544abf783bc4427b377.htm) 有需要的朋友可以下载参考-The code functions to achieve the receivi
1302write-and-read
- DS1302写读连用程序,可以设置要写的地址,Verilog语言,在板子上跑过的,可以实现功能的-DS1302 write read Ed program can be set to write the address of the Verilog language, in the board runs, can realize the function
led_rotary
- Spartan-3E实验板,基于Verilog实现旋转按钮控制八个LED灯移动方向。- a program by verilog that can control the leds in the spartan-3e lights direction by the rotary button on it.
adc_verilog
- 用verilog编写的ADC控制接口,只需根据具体ADC器件的时序图修改代码就可运行。-ADC prepared with verilog control interface, just depending on the ADC timing diagram of the device can modify the code to run.
d_e_g_dds
- 基于Verilog HDL的迟早门码元同步方案中的DDS程序,已经仿真通过,可以在FPGA开发板上实现。迟-早门方式实现码元同步在无线通信中有着广泛应用。来自华中科大。-Early-later gate of Verilog HDL-based symbol synchronization scheme in the DDS program, has been through simulation, can be achieved in the FPGA development board. F
divider
- verilog HDL编写的浮点除法器,编译通过,可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.
ARM_register
- ARM寄存器组设计的源代码,使用Verilog编程实现,可以编译仿真通过。-将中文译成英语 ARM register set design source code, the use of Verilog programming, you can compile the simulation pass.
RISC-CPU
- 用FPGA实现一个简易的CPU,采用精简指令集结构,每一条指令有16bit,高三位为指令操作数,后13位为地址,该CPU能实现8种指令操作,分别有HLT(空一个中期)ADD(相加操作)SKZ(为零跳过)AND(相与操作)XOR(异或操作)LDA(读数据)STO(写数据)JMP(无条件跳转指令)。cpu包括8个部件,分别为时钟发生器、指令寄存器、累加器、算术逻辑单元、数据控制器、状态控制器、程序计数器、地址多路器,各个部件之间的相互操作关系由状态控制器来控制,程序指令存放在初始rom中,本例程存放
spi
- 三线spi接口,用verilog实现,作为一个模块,可以接收并行数据,然后串行发送-Three Line spi interface, using Verilog implementation, as a module, can receive parallel data, and then send the serial
VerilogHDL
- 用Verilog HDL语言编写的跑马灯小程序,可直接在FPGA上运行-With the Verilog HDL language of the Marquee applet can be run directly on the FPGA
DE2_115_Audio
- FPGA开发板所带的示例程序,实现音频信号的采集,处理和输出,用verilog语言编写,可直接编译下载,非常有学习和参考价值-FPGA board comes with sample programs, audio signal acquisition, processing, and output, using Verilog language can be compiled directly download very learning and reference value! ! !
dispdecoder
- verilog写的数字频率计的显示模块,可以-written in Verilog Digital Cymometer display module can be
hdl
- 这是用Verilog HDL写的可调占空比分频控制器,可以挂在Avalon总线上使用-This is written in Verilog HDL with adjustable duty cycle frequency controller, can be hung on the Avalon bus use
even_division
- 任意基数分频VERILOG代码,经过了编译,可以修改数字改变分频。-Arbitrary base frequency Verilog code, after compilation, the figures can be amended to change the frequency.
Verilog_Coding_for_Logic_Synthesis
- 可综合的Verilog编码,很不错,学习Verilog必看。不容错过-Can be integrated Verilog coding, very good, a must-see learning Verilog. Not to be missed
Verilog_VGA
- 一个是用Verilog的程序 还可以用 -One is to use Verilog procedures also can be used
FIFO
- 用VERILOG写的FIFO程序,可以直接引用经本人测试-VERILOG written using FIFO procedures, can be directly invoked by the I test