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uart.rar
- VHDL语言编写的全功能串口模块（包含DTR，RTS等管脚），在CPLD器件上测试通过,VHDL language, full-featured serial modules (including DTR, RTS pin, etc.), in the CPLD device test
UART
- 串口实验，很好用，我还有verilog HDL VHDL CPLD EPM1270 源代码-Serial experiments, very good, and I still have the source code verilog HDLVHDL CPLDEPM1270
UART
- 串口通讯 verilog CPLD EPM1270 源代码-Serial Communication verilog CPLDEPM1270 source code
UART.ZIP
- 一个完整的用cpld实现串口功能的代码。经过验证，不经过任何修改便可使用。-serial port realized by vhdl.It has been tested and can be used with any change.
CPLD_UART
- 基于FPGA CPLD设计与实现UART,一听名字就知道，不用再说了吧，-FPGA CPLD-based Design and Implementation of UART, a name, we know that you do not say any more,
cp_uart_6
- 用CPLD驱动UART转USB芯片CP2102的verilog代码，与PC通信 包括CP2102的配置 驱动等-Using CPLD to drive the USB-UART CP2102 interface. verilog code, then communicate with PC, including the configuration and drivers, etc.
T_uart
- CPLD发送模块的实现代码,设计按键检测模块，并将键值通过构造的UART发送模块发送到串口调试工具中查看。--发送格式：1位起始位+8位数据位+1位停止位=10位-CPLD implementation of the code to send the module to design key detection module, and key by constructing the UART to send the module to send to the serial port debugg
UART-CPLD
- 使用VHDL在CPLD上设计UART的一个项目-VHDL design UART
UARTVHDL
- UART是广泛使用的串行数据通讯电路。本设计包含UART发送器、接收器和波特率发生器。设计应用EDA技术，基于FPGA/CPLD器件设计与实现UART。-UART is a widely used serial data communication circuit. The design includes UART transmitter, receiver and baud rate generator. Application of EDA design technology based o
CPLD_V105
- epm240系列cpld的配置文件，实现cpld对flash，uart和sdram的控制等-epm240 series cpld profile, to achieve cpld on the flash, uart and the sdram of the control
miniuart2
- 用ＶＨＤＬ在CPLD/FPGA上实现与PC机的RS232通信-This UART (Universal Asynchronous Receiver Transmitter) is designed to make an interface between a RS232 line and a wishbone bus, or a microcontroller, or an IP core. It works fine connected to the serial port of a
uart_R_S
- 用CPLD实现串口UART的收发功能，主要是时序的实现。晶振20MHz.-UART Serial Port with a CPLD to send and receive functions, mainly the timing of implementation. The device s Crystal is 20MHz.
uart
- CPLD+MCU电压采集系统 测试程序-CPLD+ MCU voltage acquisition system
uart
- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x104，对应的波特率是 --9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步.程序的工作过程是：串口处于
uart-code-(Verilog)
- uart 源码 Verilog CPLD -uart code Verilog CPLD
UART
- verilog语言编写在CPLD上构建一个遵循串口通信规范的程序-verilog language serial procedures
cpld-urat-vhdl
- 基于CPLD的VHDL UART代码，串行异步通信，含代码及仿真图-Based on the CPLD VHDL UART code, serial asynchronous communication, including code and simulation diagram
UART
- 串口通讯，光纤通讯，需要中间一个CPLD的转换，这个转换需要一种自适应的算法。-Serial port and serial port and optical fiber communication and optical fiber communication serial communication serial port and serial port and optical fiber communication and optical fiber communication seria
UART
- 使用标准VHDL编写的RS232协议，可在CPLD或者FPGA上直接实现串口通信功能。-use VHDL to implement RS232 protocol, which can be used in CPLD or FPGA
uart
- 通过CPLD，可以进行和电脑的串口通讯。-By CPLD, and computers can be serial communication.