搜索资源列表
32mips-cpu
- 基于32为MIPS指令设计的cpu,32 for the MIPS instruction based on the design of the cpu-32 for the MIPS instruction based on the design of the cpu
alu
- 加法器源码 CPU设计专用 VHDL实现-Source adder VHDL CPU designed to achieve specific
CPU
- mips系列,CPU的Verilog语言设计,自己写的-mips series, CPU of the Verilog language design, to write their own
CPU-design
- 使用VHDL语言开发的CPU硬布线设计,在实验电路可以使用加法,和减法与或等简单操作-CPU using VHDL language development of hard-wired design, the circuit can be used in the experimental addition, and subtraction or other simple operations with
POC-Project
- 系统总线与打印机之间的借口:并行输出控制器POC的设计。涉及POC与CPU,POC与printer之间的握手操作。-Between the system bus and an excuse for the printer: parallel output controller POC design. Involved in POC and CPU, POC and the printer handshake between the operations.
cpu-design
- VHDL设计的一个可综合的精简指令集的CPU,加上外围模块,类似与51单片机,当然还缺少很多功能,只是雏形,供大家交流-VHDL design of an integrated RISC CPU, coupled with external modules, exhausted and 51 single-chip, of course, the lack of many features, but prototype for all to share
CPU-tool-chain-design
- 摘要:EDA技术的成熟和进步,缩短了微处理器硬件设计和综合的周期。同时,开发工具链设计的自动化,已成了高效率、高质量嵌入式微处理器设计的重要内容。本文提出了采用体系结构描述语言(ADL)实现微处理器开发工具链自动设计的有效方法。针对ADL描述流水线的局限性,进行了扩展改进,因而使改进后的ADL能用来直接描述流水线。新方法在CK幸CORE开发工具链设计中的应用表明,比用GNU工具链功效有了显著提高。-Abstract: EDA technologies mature and progress, r
zxcpu
- 用VHDL语言设计了一个含10条指令的RISC处理器。假定主存可以在一个始终周期内完成依次读写操作且和CPU同步,系统使用一个主存单元。处理器指令字长16位,包含8个通用寄存器,1个16位的指令寄存器和一个16位的程序记数器。处理器的地址总线宽度16位。数据总线宽度16位,取指和数据访问均在一跳蝻数据总线。处理器支持包含LDA,STA,MOV,MVI,ADD,SUB,AND,OR,JZ,JMP十条指令。其中仅有LDA和STA是访存指令。-VHDL language design with a R
MSP430-to-CPU-card-interface-
- MSP430单片机与CPU卡接口函数设计-MSP430 MCU and CPU card interface function design
vhdl_16CPU
- 16位CPU设计,采用VHDL语言,自带测试汇编语言,能实现基本运算和移位、跳转等操作-16-bit CPU design, using VHDL language, self-test assembly language, to achieve the basic operations and shift operations such as jump
cpu
- 以ISE为平台设计的单时钟CPU,实现最基本的5条指令(R、LW、SW、BEQ、J) -ISE as a platform to design single-clock CPU, 5 to achieve the most basic instructions (R, LW, SW, BEQ, J)
cu
- 基于quartus的CPU设计中核心部件,控制存储器的架构-Quartus CPU design based on the core components, control memory architecture
cpu
- 单周期和流水dsp cpu的设计 及foword的插入-Single-cycle and water dsp cpu plug design and foword
CPU--design
- 该文档很好的介绍了8位cpu的设计,代码非常详细,很好的参考资料-The document describes a good design of 8-bit cpu, code is very detailed, good reference
cpu_verilog_vhdl
- CPU核verilog、VHDL实现(两个8051带文档 , or12000 ) 以及cpu设计教程-Personal collection of the CPU core (with two 8051 documents, or12000) plus cpu design tutorials
MIPS_CPU_OR2000
- MIPS架构的开发的CPU软核OR2000 verilog实现,MIPS体系结构cpu设计入门参考-The development of the MIPS architecture CPU soft core OR2000
s5pv310--CPU-Board-a-Main-Board-
- cortex A8 S5PV210 设计参考原理图,PDF文档-cortex A8 S5PV210 reference design schematics, PDF documents
FPGA-and-cpu
- FPGA与单片机的串行通信接口的程序设计-FPGA and cpu
soc
- 精简的单周期CPU设计代码,适合SOC设计初学者,基本模块包括LED,switch bar,seven segment-Streamlined single-cycle CPU design code for SOC design for beginners, basic modules include
RISC_CPU
- 一个简单CPU设计,可以让读者在计算机组成原理和verilog语言方面受益-A simple CPU design, allows the reader to the computer principles and Verilog language benefit