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SOPC Builder创建的CPU，能够满足简单的VHDL软件仿真-SOPC Builder to create the CPU, to meet the simple VHDL software simulation
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实现简单CPU功能的源码，可以实现加减乘除和移位功能，VHDL代码，程序运行在MAX PULS和Quartua上。-The purpose of this project is to design and simulate a parallel output controller (POC) which acts an interface between system bus and printer. The Altera’s Maxplus Ⅱ EDA tool is recommended
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利用vhdl模拟实现CPU的功能，实现其中的加减乘除等多种运算-CPU utilization of vhdl simulation of the realization of the function, the realization of which, such as addition and subtraction, multiplication and division multiple computing
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微程序控制器部件实验，使用VHDL语言使用Quartus测试通过，模拟CPU-Micro-program controller component experiments, the use of VHDL language use Quartus test, simulation CPU
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包含CPU每部分器件的编写，通过改写RAM内容，可实现CPU简单运算的仿真-Some devices include the preparation of each CPU, RAM by rewriting the content, enabling easy operation simulation CPU
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poc即为cpu与外部设备，比如打印机的接口，用VHDL的编程来实现poc功能的仿真-poc is the cpu with an external device, such as the printer' s interface, programming with VHDL simulation capabilities to achieve poc
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并行输出控制器，实现CPU与打印机之间的通信，程序基于VHDL语言，内附完整实验报告与仿真图像-The purpose of this project is to design and simulate a parallel output controller (POC)which acts an interface between system bus and printer. The Altera’s Quartus II EDA tool is recommended and provid
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一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
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16位的5级流水线cpu 采用vhdl代码 modelsim编译仿真-5-stage pipeline 16-bit cpu compiled simulation using modelsim vhdl code
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VHDL的CPU仿真与实现 很好的源代码介绍-The CPU simulation and VHDL source code to achieve a good descr iption
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基于VHDL的简单CPU模型的代码，包含十个原件。已经过仿真河综合-VHDL code for a simple CPU model-based, contains ten originals. River Comprehensive simulation has been
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基于VHDL的简易CPU设计，可以实现加、减、乘三种运算，模拟CPU的运算过程通过指令实现运算-Simple CPU design based on VHDL, three operation can realize add, subtract, multiply, simulation of the CPU operation process operation was achieved by instruction
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a very useful vhdl source code for simulation and test the parwan cpu navabi vhdl book-a very very useful vhdl source code for simulation and test the parwan cpu navabi vhdl book
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使用QuartusII软件，利用VHDL语言设计实现CPU,其中包含时序图仿真。-Using software QuartusII, using VHDL language to design the CPU, which contains sequence diagram simulation.
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设计一个模型机，具体设计要求如下：
（1）设计指令系统，要求有取数指令、加法指令、跳转指令、停机指令等
（2）设计指令格式、微指令格式 、微程序 、时序电路 、数据通路，完成cpu的设计。
（3）利用模块化设计，分别设计存储器模块、运算器模块、时序电路模块、微程序控制器模块、显示模块等，最后进行系统的顶层设计，完成复杂模型机的设计与实现测试
（4）根据任务，完成主程序的设计，同时把主程序翻译成目标代码，写入主存，仿真下载测试。(Design a model machine, th
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