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CIC_deci4.rar
- cic抽取滤波器ip核，用于射频采样数字下变频模块的核心数字信号处理部分.此ip核已经过ise10.2验证,CIC decimation by 4 filter，used in Direct RF sampling of GPS signal. the core dsp block in a frondend design
CIC_DEC
- CIC抽取滤波器设计，CIC滤波器采用5阶8倍抽取。-CIC decimation filter design, CIC filter order of 8 times 5 samples.
cic_dec_8_three
- 8位三级CIC抽取滤波器，VHDL语言版~-8 three-CIC decimation filter
design
- The verilog implementation of 8-point FFT in verilog. Radix 2 Decimation in Frequency.
CIC_DEC_3
- CIC抽取滤波器设计，CIC滤波器采用5阶3倍抽取。-CIC decimation filter design, CIC filter order 3 times 5 samples.
CIC_DEC_4
- CIC抽取滤波器设计，CIC滤波器采用5阶4倍抽取。-CIC decimation filter design, CIC filter order 4 times using 5 samples.
CIC_DEC_6
- CIC抽取滤波器设计，CIC滤波器采用5阶6倍抽取。-CIC decimation filter design, CIC filter stage 6 times 5 samples.
Enhancing_ADC_resolution_by_oversampling
- 使用过采样的方法提高AVR的模数转换器的精度 "过采样和抽取"的方法，以及应用该方法而非外部的模数转换器达到提高精度的目的时所应满足的条件。-This Application Note explains the method called "Oversampling and Decimation" and which conditions need to be fulfilled to make this method work properly to get achieve higher
fft1drad2cmpx_121900
- ADI 的 ADSP_BF533 FFT程序-This file contains the code for the implementation of FFT. The Algorithm used is Decimation in Time. For the optimization point of view, the whole computation of butterfly signal flow has beee
cic_dec_8_five
- CIC抽取滤波器，抽取系数8,verilog版本，用于数字下变频-CIC decimation filter, extraction coefficient of 8, verilog version, for digital down-conversion
fir_dec3
- FIR抽取滤波器，抽取系数3，Verilog版本，数字下变频-FIR decimation filter, extraction coefficient of 3, Verilog version of the digital down-conversion
cic
- 抽取滤波的Verilog实现，经测试可用-Decimation filter
COlD_FFT
- The VHDL implementation of 8-point FFT in VHDL. Radix 2 Decimation in Frequency-The VHDL implementation of 8-point FFT in VHDL. Radix 2 Decimation in Frequency It is very good
FFT
- The VHDL implementation of 8-point FFT in VHDL. Radix 2 Decimation in Frequency-The VHDL implementation of 64-point FFT in VHDL. Radix 2 Decimation in Frequency i am found of it.It s really very good!
datasheet
- Implementing the Radix-4 Decimation in Frequency (DIF) Fast Fourier Transform (FFT) Algorithm Using a TMS320C80 DSP
cic-1
- cic滤波器2倍抽取verilog代码及testch-cic filter decimation verilog code and testch
FFT
- 基2按时间抽取倒位序算法，我自己编写注释的，你可以看看。-Radix-2 decimation-in-time inversion sequence algorithm
HalfbandDec
- 基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。-Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.
DDC_FPGA
- 基于FPGA的数字下变频器（DDC）的设计,将采样得到的高速率信号变成低速率基带信号，以便进行下一步的信号处理。由NCO、数字混频器、低通滤波器和抽取滤波器四个模块组成。采用自编的加法树乘法器，提高乘法运算效率。-Design based on FPGA digital downconverter (DDC), the high-speed signal will be sampled baseband signal into a low rate for the next step in th
24CIC
- 基于fpga的抽取CIC滤波器设计,采用verilog编写，24抽取,仿真通过-Fpga-based CIC decimation filter design using verilog written, 24 extraction