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CIC_deci4.rar
- cic抽取滤波器ip核，用于射频采样数字下变频模块的核心数字信号处理部分.此ip核已经过ise10.2验证,CIC decimation by 4 filter，used in Direct RF sampling of GPS signal. the core dsp block in a frondend design
CIC_DEC
- CIC抽取滤波器设计，CIC滤波器采用5阶8倍抽取。-CIC decimation filter design, CIC filter order of 8 times 5 samples.
cic_dec_8_three
- 8位三级CIC抽取滤波器，VHDL语言版~-8 three-CIC decimation filter
design
- The verilog implementation of 8-point FFT in verilog. Radix 2 Decimation in Frequency.
CIC_DEC_3
- CIC抽取滤波器设计，CIC滤波器采用5阶3倍抽取。-CIC decimation filter design, CIC filter order 3 times 5 samples.
CIC_DEC_4
- CIC抽取滤波器设计，CIC滤波器采用5阶4倍抽取。-CIC decimation filter design, CIC filter order 4 times using 5 samples.
CIC_DEC_6
- CIC抽取滤波器设计，CIC滤波器采用5阶6倍抽取。-CIC decimation filter design, CIC filter stage 6 times 5 samples.
cic_dec_8_five
- CIC抽取滤波器，抽取系数8,verilog版本，用于数字下变频-CIC decimation filter, extraction coefficient of 8, verilog version, for digital down-conversion
fir_dec3
- FIR抽取滤波器，抽取系数3，Verilog版本，数字下变频-FIR decimation filter, extraction coefficient of 3, Verilog version of the digital down-conversion
cic
- 抽取滤波的Verilog实现，经测试可用-Decimation filter
COlD_FFT
- The VHDL implementation of 8-point FFT in VHDL. Radix 2 Decimation in Frequency-The VHDL implementation of 8-point FFT in VHDL. Radix 2 Decimation in Frequency It is very good
FFT
- The VHDL implementation of 8-point FFT in VHDL. Radix 2 Decimation in Frequency-The VHDL implementation of 64-point FFT in VHDL. Radix 2 Decimation in Frequency i am found of it.It s really very good!
datasheet
- Implementing the Radix-4 Decimation in Frequency (DIF) Fast Fourier Transform (FFT) Algorithm Using a TMS320C80 DSP
cic-1
- cic滤波器2倍抽取verilog代码及testch-cic filter decimation verilog code and testch
HalfbandDec
- 基于FPGA开发的11阶半带升余弦FIR滤波器，用在阅读器基带滤波时的抽取滤波器使用，采用verilog语言实现。-Raised cosine FIR filter based FPGA development 11 order of half-band decimation filter used in reader baseband filtering, using verilog language implementation.
DDC_FPGA
- 基于FPGA的数字下变频器（DDC）的设计,将采样得到的高速率信号变成低速率基带信号，以便进行下一步的信号处理。由NCO、数字混频器、低通滤波器和抽取滤波器四个模块组成。采用自编的加法树乘法器，提高乘法运算效率。-Design based on FPGA digital downconverter (DDC), the high-speed signal will be sampled baseband signal into a low rate for the next step in th
24CIC
- 基于fpga的抽取CIC滤波器设计,采用verilog编写，24抽取,仿真通过-Fpga-based CIC decimation filter design using verilog written, 24 extraction
CIC_filter_implement
- 实现CIC抽取滤波器，在多速率通信中经常需要用到的CIC抽取滤波器-CIC decimation filter implemented in the multi-rate communications often need to use the CIC decimation filter
CIC_4ORDER
- 4阶24倍抽取CIC滤波器的verilogHDL源代码，仿真测试代码及相关资料-4-order CIC decimation filter 24 times verilogHDL source code, simulation test code and related information
code-pour-decim-poly
- this code is for a decimation filter with polyphase structure , so the original filter is decomposed by 5 filters which is the decimation factor in that case and each of them is selected each Fs/5