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c_xapp753
- 使用 EMIF 将 Xilinx FPGA与 TI DSP 平台接口
EMIFXilinxFPGATIDSP
- 通过EMIF连接fpga与dsp的代码
FIFO_EMIF.rar
- 实现FPGA通过EMIF总线给DSP定期发送数据的功能,FPGA implementation through the EMIF bus regularly send data to the DSP function
EMIF_COM.rar
- 实现FPGA与DSP之间通信的接口,利用DSP的标准EMIF接口,the interface for TI DSP and Xilinx s FPGAs
cis_100dpi_dsp
- 程序实现了采用CIS+AD9822+FPGA的结构形式对人民币进行采集。然后把采集到得数据通过EMIF接口传送给DSP。已通过调试-Program implements the use of CIS+ AD9822+ FPGA structure in the form of the RMB is collected. Then the data collected was transmitted through the EMIF interface to the DSP. Has passed
XilinxisdisclosingthisSpecification
- Xilinx is disclosing this Specification ? 第 1 章“EMIF 概述”，概述 Texas Instruments EMIF。 ? 第 2 章“Virtex-II 系列或 Spartan-3 FPGA 到 EMIF 的设计”描述将 TI TMSC6000 EMIF 连接到 Virtex?-II 系列或 Spartan?-3 FPGA 的实现。 ? 第 3 章“Virtex-4 FPGA 到 EMIF 的设计” 描述将 TI TMS320C6
write_io
- DSP EMIF 扩展io程序 DSP EMIF 扩展io程序-DSP EMIF procedures to expand io expansion io procedures DSP EMIF
write_rd
- 关于VHDL的 关于DSP的 emif-On VHDL on the DSP s EMIF
EMIF
- A code for dsp6416 in CCSv3.1 that represent the use with EMIF.
xapp753
- FPGA Interface to the TMSC6000 DSP Platform Using EMIF
DSP-External-Memory-Interface-Module
- EMIF是DSP嵌入式系统中重要的外扩接口，往往连接大容量/高速存储器、并行AD/DA、外扩特殊功能芯片，甚至连接FPGA或者ASIC。-EMIF is a DSP embedded system is an important external expansion interface, often connect large-capacity/high-speed memory, parallel AD/DA, outside the extended special function chi
TestDSPFPGA
- 一个用于DSP和FPGA通讯的测试程序，FPGA用EMIF接口接入-A test program for the DSP and FPGA communication, FPGA with the EMIF interface access
eetop.cn_emif_brg
- fpga与DSP通过emif接口通信，fpga内部通过fifo进行数据缓存-fpga with the DSP through emif interface communication, fpga internal data cache by fifo
c6701
- 航空板上TMS320C6701 DSP配置EMIF，读写SDRAM FLASH 和FPGA等外围电路的源码-Aviation board TMS320C6701 DSP configuration EMIF, literacy SDRAM FLASH and FPGA source code and other peripheral circuits
emifa_ram
- FPGA与DSP的EMIF通信，EMIF的RAM这方面相应的程序-FPGA and DSP EMIF communication
FPGA2-DSP2-EDMA
- 例程是FPGA通过EMIF给DSP发送数据，里面包含了一个简单的状态机和一个基于IP核的fifo，适合初学者-Routine is the FPGA to send data to the DSP via EMIF, which contains a simple state machine and an IP-based core fifo, suitable for beginners
6f041ed721eb
- 简单的dsp与fpga接口代码。emif-Dsp and fpga simple interface code. emif
EMIF
- EMIF接口调试代码，使用的是Verilog语言，FPGA与DSP通信，测试成功-EMIF interface debugging code that USES the Verilog language, FPGA and DSP communication, testing success
FPGA_emif
- 接口模块，通过对高位地址的编码可实现在一个FPGA中配置四个独立的功能模块，每个功能模块具有一个带FIFO的输出口和13个独立的可由DSP读写的寄存器，寄存器功能可自定义。模块还包含两个全局寄存器，可实现全局复位，中断等功能。该模块以应用于实际的项目中，目前运行良好-FPGA to emif
EMIF
- 这是DSP的EMIF总线和FPGA通信的实例，已经测试能用-This is DSP EMIF bus and FPGA communication as an example, has been testing can be used