搜索资源列表
Qcalc
- 一种基于FSM框架的计算器状态机源码，非常有利于大家对状态机的理解-status machin
t3_sdram
- 完成sdram读写操作，并附有测试脚本文件，已通过后仿验证。该程序主要包括上电初始化模块，刷新模块，读、写模块等，并采用FSM控制所有模块，完成数据的读写操作-Sdram read and write operations to complete, with a test scr ipt file has been verified through simulation. The program includes power-on initialization module, refresh m
fsm
- 有限状态机的一种实现框架，更健壮，更易于表达。-An implementation framework of finite state machines, more robust and easier to express.
fsm
- verilog四状态状态机 带异步清零端和测试向量 mealy型状态机 很好用哦 -verilog four state machine with asynchronous clear end and test vectors mealy-type state machine oh well
FSM
- it explains how to write the statemachins
CoG
- Semi-functional FSM and ROM for Xilinx CPLD to drive ST7565R based off Digikey example
UpDownCounter_FSM
- This code is an Up Down Counter in FSM using Verilog HDL.
seg
- 可以很好学习的学习状态机！学习逻辑能力,提高自己的代码书写能力！-FSM study,if you like study vhdl,you could download this zip to study
Exp15_FSMKEY
- 基于STM8S105C6T6 的FSM按键扫描，完全状态机，支持 按下 长按 连发 抬起，最多256个按键。超小RAM-STM8S105C6T6 of FSM based key scanning, complete state machine, press the press and bursts of support to lift up to 256 keys. Ultra-small RAM
avr_keypad
- 1.基于FSM(有限状态机)扫描独立按键,并带 长按 功能； 2.基于FSM扫描4*4矩阵键盘。-1. Based on FSM (finite state machine) scan separate buttons, and with a " long press" function 2. Based on the FSM 4* 4 matrix keyboard scanning.
lab7_2_new
- 移动信息工程学院实验课程源码：用FSM实现soda_machine(自动售货机)-Use verilog to implemwnt a soda_machine
lab9_2
- 用verilog实现更高级的交通灯：增加游行模式。实质上是对米粒状态机的掌握-An implementation in verilog on Mealy FSM
fsm
- 三段式状态机的典型写法，verilog实现-The three section type of typical state machine method, Verilog implementation
autosell
- 自动售货机程序，以Verilog三段式描述方法描述有限状态机FSM，编译及输出正常-Vending machine program, describe the method described in Verilog three-finite state machine FSM, compile and output normal
fifo
- FIFO FSM Implementation
FSM
- 序列检测器，采用有限状态机实现，检测特定序列“101011”- Sequence detector, finite state machine, detection of a specific sequence 101011
FSM
- 序列检测器，采用移位寄存器实现，检测特定序列“101011”-Sequence detector using a shift register implementation, detection of a specific sequence 101011
Mojo-FSM
- Finit state machine proce-Finit state machine process
fsm
- verilog语言，有限状态机实现的序列检测器-verilog language, finite state machine sequence detector
image_ver_main
- The design of multi level sensor is mostly based on FSM controller-The design of multi level sensor is mostly based on FSM controller