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基于CPLD-FPGA的半整数分频器的设计
- 基于CPLD-FPGA的半整数分频器的设计，用于设计EDA-based CPLD-half FPGA integer dividers in the design, design for EDA
DSP实时调试rtdxint
- 有关RTDX应用的例子。使用时请打开命令提示符窗口，再运行release 目录下的rtdxint.exe程序。此程序从COM接口指定的RTDX Channel读取一个整数。-the RTDX application examples. Use open the command prompt and then run the release directory rtdxint.exe procedures. This procedure from the COM interface desi
FPGAprogram2
- 半整数分频器电路的VHDL源程序，供大家学习和讨论。 -half-integer frequency divider circuit VHDL source code for all learning and discussion.
pic32
- 用PIC单片机实现64位整数的运算,在控制算法中经常要用到-PIC MCU 64-bit integer arithmetic, the control algorithm is used often
MAR1PSD
- Routine mar1psd: To compute the power spectum by AR-model parameters. Input parameters: ip : AR model order (integer) ep : White noise variance of model input (real) ts : Sample interval in seconds (real) a : Complex array of AR parame
digitalsystemDesign
- 第7章数字系统设计实例 7.1 半整数分频器的设计 7.2 音乐发生器 7.3 2FSK/2PSK信号产生器 7.4 实用多功能电子表 7.5 交通灯控制器 7.6 数字频率计-Chapter 7 Digital System Design Example 7.1-integer dividers designed Music Generator 7.2 7.3 2F SK/2PSK Signal Generator 7.4 Table practical multi-f
at91c
- 嵌入式系统开发用源代码 包含At91C arm芯片相关各种例程 包括整数性能测试,浮点测试,硬件驱动等-embedded systems development using the source code contains At91C arm chip related various routines including integer performance measurement Ban, floating point tests, such as hardware drivers
FtoI
- 一个浮点数和整数互相转换的测试程序, 不依赖于浮点库, 效率高,适合移植于单片机.-an integer and float transferable test procedure is not dependent on the floating-point, high efficiency, MCU suitable for transplant.
feizhenshu
- 非整数分频器 分频系数为无限不循环小数 vhdl-non-integer frequency divider coefficient of circulator is not unlimited vhdl
renyizhengshufenpingdeVHDLdaima
- 本文件是实现任意整数分频的VHDL代码,愿与大家分享!-this document is arbitrary integer frequency VHDL code, and is willing to share with you!
4_bit_calculator
- 单片机计算器 用c写的 用proteus仿真成功 并且实际硬件电路调试也成功 只能计算整数-SCM calculators used by the write c proteus successful simulation and actual hardware circuit debugging also successfully only integer computation
ClockOut
- 通过VERILOG编程，实现FPGA任意整数分频的源代码-through verilog programming, FPGA arbitrary integer frequency of the source code
VHDLnf
- VHDL实现任意整数分频，--只要把n设置成你要分频的数值就可以了-VHDL arbitrary integer frequency, -- n as long as you want to set the frequency of the numerical breakdown on the
Bipolar-pid-integer-
- 双极性pid 单极性就是输出只有整数没有负数，双极性有负数，比如一个温度控制系统，只有加热或者只有制冷，这就是单极性，又有加热也有制冷这就是双极性-Bipolar pid integer not only unipolar output is negative, bipolar have a negative, such as a temperature control system, only heating or only cooling, which is unipolar, there
dct2
- 这个是一个基于FPGA的数字图像的整数DCT变换程序，程序高性能地实现了2维DCT变换。-This is an FPGA-based digital image of the integer DCT transform process and procedures to achieve high-performance 2-D DCT transform.
Fusion
- Fusion using integer wavelet transform implemented in C for BF532 Processor uisng VisualDSP++5.0
integerwavelettransformreconstruction
- integer wavelet reconstruction
Logic_and_Integer_Programming
- Logic and Integer Programming. This book combines two related topics which are usually covered in separate texts,namely logic and integer programming (discrete ptimisation). These two subjects have close connections and each is applicable to the o
Verilog_integer_reg
- 深入探讨verilog中integer与reg两者的区别，从综合与实现的角度介绍-Depth in the integer and reg verilog difference between the two, from the point of introduction and implementation of comprehensive
An-integer-
- 一个整数，它加上100后是一个完全平方数，再加上168又是一个完全平方数，请问该数是多少？ 1.程序分析：在10万以内判断，先将该数加上100后再开方，再将该数加上268后再开方，如果开方后 的结果满足如下条件，即是结果-An integer that is a perfect square plus the 100, plus the 168 is a perfect square, what is the number? 1 Program Analysis: less