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基于CPLD-FPGA的半整数分频器的设计
- 基于CPLD-FPGA的半整数分频器的设计，用于设计EDA-based CPLD-half FPGA integer dividers in the design, design for EDA
FPGAprogram2
- 半整数分频器电路的VHDL源程序，供大家学习和讨论。 -half-integer frequency divider circuit VHDL source code for all learning and discussion.
digitalsystemDesign
- 第7章数字系统设计实例 7.1 半整数分频器的设计 7.2 音乐发生器 7.3 2FSK/2PSK信号产生器 7.4 实用多功能电子表 7.5 交通灯控制器 7.6 数字频率计-Chapter 7 Digital System Design Example 7.1-integer dividers designed Music Generator 7.2 7.3 2F SK/2PSK Signal Generator 7.4 Table practical multi-f
feizhenshu
- 非整数分频器 分频系数为无限不循环小数 vhdl-non-integer frequency divider coefficient of circulator is not unlimited vhdl
renyizhengshufenpingdeVHDLdaima
- 本文件是实现任意整数分频的VHDL代码,愿与大家分享!-this document is arbitrary integer frequency VHDL code, and is willing to share with you!
ClockOut
- 通过VERILOG编程，实现FPGA任意整数分频的源代码-through verilog programming, FPGA arbitrary integer frequency of the source code
VHDLnf
- VHDL实现任意整数分频，--只要把n设置成你要分频的数值就可以了-VHDL arbitrary integer frequency, -- n as long as you want to set the frequency of the numerical breakdown on the
三种16位整数运算器的ALU设计方法
- 三种16位整数运算器的ALU设计方法，调用库函数74181（4位ALU），组成串行16位运算器。(用74181的正逻辑) B．调用库函数74181和74182，组成提前进位16位运算器。(用74181的正逻辑) 注意：调74181库设计，加进位是“0”有效，减借位是“1”有效，所以最高位进位或借位标志寄存器要统一调整到高有效 C．用always @，case方式描述16位运算器。,Three 16-bit integer arithmetic logic unit of the ALU
RTL
- 256位有符号整数乘法器，个人学习时编写，接口为IPBUS，用verilog语言编写-256-bit signed integer multiplier, when writing individual learning, the interface IPBUS, with verilog language
sqrt32
- verilog源代码，用于开根号计算（32位）-sqrt32.v sqrt of 32-bit integer, Verilog source
divider
- 由VHDL撰写的强大多功能除频器，只需由上方参数载入除频数N及N的宽度(2的次方)即可使用。 可以除以任意整数，包含奇数。-Written by the powerful multi-functional VHDL divider, just above the parameters included in addition to the frequency width of N, N-(2 power) can be used. Can be divided by any integer,
mult8_csdn
- 用verilog语言编写的8位乘法器，完成了8位二进制的整数乘法，供大家参考-Verilog language with 8-bit multiplier, completed the 8-bit binary integer multiplication, for your reference
cnt8bc
- 8位加减带异步复位计数器，使用双向输入管脚- Design an 8-bit up and down synchronous counter in VHDL with the following features: The same ports are used for signals to be inputted and outputted. The ports are bi-directionally buffered. The counter is with an asynch
VHDL
- 一个实现整数分频的VHDL代码，只要把n设置成你所需要的分频的数值就行-A realization of an integer divider of the VHDL code, as long as the n set you need the sub-frequency values on the line
divider
- 该模块为分频器，将1KHZ的时钟频率分频成每分钟一次的时钟频率 事实上，该源码可以实现任意整数的分频，主要让N的值设置好相应的数字-The module for the divider, the clock frequency 1KHz frequency per minute into the first clock frequency In fact, the source can be any integer frequency, mainly to allow the value o
dividend4
- 本设计是一个八位被除数除以四位除数，得到不超过四位的商的整数除法器。被除数、除数、商和余数都是无符号整数。-The design is an eight dividend divided by the divisor of four, to be not more than 4 business integer divider. Dividend, divisor, and remainder are unsigned integers.
dividers
- verilog格式的除法器，试过了，很好用，再也不要为触发器发愁了-Verilog format divider, tried, very good, and no longer for the flip-flop not to worry about the
dct2
- 这个是一个基于FPGA的数字图像的整数DCT变换程序，程序高性能地实现了2维DCT变换。-This is an FPGA-based digital image of the integer DCT transform process and procedures to achieve high-performance 2-D DCT transform.
Logic_and_Integer_Programming
- Logic and Integer Programming. This book combines two related topics which are usually covered in separate texts,namely logic and integer programming (discrete ptimisation). These two subjects have close connections and each is applicable to the o
Verilog_integer_reg
- 深入探讨verilog中integer与reg两者的区别，从综合与实现的角度介绍-Depth in the integer and reg verilog difference between the two, from the point of introduction and implementation of comprehensive