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Block_addgen
- Interleaved Block address generator (customized block size and interleaving strip size).
CONVOLUTIONAL_INTERLEAVER
- DVB数据交织,交织深度I=12,已得到应用!-DVB data interleaving, interleaving depth I = 12, has been applied!
OFDM_FPGA
- OFDM的FPGA实现 内含卷积编码 交织，频偏检测 完整的OFDM实现代码 -The FPGA contains OFDM convolutional coding to achieve interleaving, OFDM frequency offset detecting the full implementation code
jiaozhi_64
- VHDL语言实现按字节块交织，实现每64字节进行一次交织。-The VHDL language byte block interleaving, once every 64 bytes intertwined.
卷积交织器解交织器设计
- 交织技术通常分为分组交织和卷积交织。分组交织过程是数据先按行写入，再按列读出；解交织过程是数据先按列写入，再按行读出。其特点是结构简单，但数据延时时间长，而且所需的存储器比较大。(Interleaving techniques are usually divided into packet interleaving and convolution interleaving. Packet interleaving process is the first data written by row,