搜索资源列表
ASYfifo
- 这是FIFO程序，开发工具是ISE或QUartus。-procedures, development tools or QUartus ISE.
16×4bitFIFO
- 16×4bit的FIFO设计,VHDL语言编的的，能在ISE上仿真出来结果。
FIFO
- it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a
FIFO
- This code is a FIFO memory vhdl developed in ISE Software
ASYNCFIFO
- 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
fifomodule
- 定义了一个FIFO和相关的读写功能,比较实用,可直接作为模块使用-define a FIFO that contains the relative read and write functions, and it can be used as module directly in ISE.
mypro_synfifo
- 基于IP核RAM的同步fifo设计，工程使用Xilinx的开发软件ISE-RAM-based synchronization fifo IP core design, engineering, software development using Xilinx ISE
fifo
- verilog实现fifo，ise中仿真，chipscope调试-verilog achieve fifo, ise in the simulation, chipscope debugging
fifo_ip
- 本程序是利用ise平台提供的IP核设计出的fifo，通过过上机运行检测。-This procedure is to use ise platform provides IP core design a fifo, passed through the machine running the test.
GTX_AURORA_MAIN
- 将数据从板卡网口(Ethernet Mac)经过fifo发至GTX高速串行口 ISE -The data from the network interface card (Ethernet Mac) through fifo GTX sent to high-speed serial port ISE