搜索资源列表
m15
- 扩频通信M序列,编码,通用VHDL语言-M sequence spread spectrum communication, coding, generic VHDL
pseudorandom
- 伪随机m序列产生的VHDL语言程序- program in VHDL language for generating pseudo-random m sequence
mcode
- 用VHDL语言生成m序列,进行扩频。m序列是10级的。-m sequence
m.rar
- 扩频接收机设计的部分,一个用vhdl语言编写的m序列生成器,,A language with vhdl generator sequence m
m_vhdl
- 伪随机序列发生器的vhdl算法 设计一个伪随机序列发生器,采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值(程序中设定好四种非零初值可选)-m sequence vhdl
m
- vhdl,序列信号发生器,发出11101010,可更改为任意序列-vhdl, sequence signal generator, issued 11.10101 million, you can change an arbitrary sequence of
interweave_1
- 用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入,按列读出的方法实现。主要包括:信源信号产生(20位的m序列),交织器,解交织器。为实现流水线的操作,采用了两个交织器和两个解交织器,当一个写入数据的时候,另一个读出数据。-Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by colu
hanming
- 产生m序列作为输入信号,能够实现(7,4)汉明码编码和译码功能。同时,还有加噪模块。 在QuartusII工作环境下使用-M sequence generated as the input signal, can be achieved (7,4) hamming code encoding and decoding functions. There are also additional noise modules. Working environments in the QuartusI
hamming_encodeadecode
- 用Verilog语言编写的对m序列进行汉明码编译码的程序。具体实现为产生m序列后对其进行(7,4)汉明码编码并加错,然后将其纠错译码并输出,详细过程见仿真。-Written by Verilog m sequence of procedures for coding and decoding Hamming codes. Concrete realization of m sequence to produce its (7,4) hamming code and a mistake, and
2mxulie
- 基于CPLD的数字通信系统 2m序列 用VHDL产生 2m序列信号-CPLD-based digital communications systems using VHDL generate 2m sequence signal sequence 2m
verilog_m
- 用verilog生成的m序列,包含四个.v的文件-verilog m sequence
cml
- 基于Verilog的数字基带通信系统 3. 项目描述:本系统为通信原理课程设计课题之一,用Verilog语言编写数字基带通信系统的应用程序,完成P=31的m序列的生成,并进行HDB3编码传输,在接收端进行译码接收。-Verilog-based digital baseband communication system 3. Project Descr iption: The system is one of the topics Communication Theory course des
m_serial
- 本实验利用单片机实现m序列的输出,其移位寄存器的长度为3 - 8可循环调节。单片机板上按键KEY1实现级数n的循环自加,按键KEY2实现级数n的循环自减,输出口P1^4输出m序列周期同步信号,输出口P1^6输出相应的m序列。-In this study, the use of single-chip microcomputer m sequence of output, the length of the shift register 3- 8 can be recycled adjustabl
VHDlsheji
- 本文介绍了一种使用VHDL 设计多波形m 序列 发生器的原理与实现方法。-This paper presents a VHDL design using multi-waveform m sequence generator principle and realization method.
fufenjieqi
- 基于FPGA的复分接器,包括了M序列码的产生,2路数据复接,数据分接(包括巴克码的判断)。-FPGA-based compound splitters, including M sequence code generation, 2 channel data multiplexing, data tap (including the Barker code to judge).
jiaozhibianmaqi
- 基于单片机的交织编码器,采用汇编语言编写,用D触发器产生m序列。-Encoder based on single chip interleaving, using assembly language, using D flip-flop produces m sequence.
m_vhdl
- 设计一个伪随机序列发生器,采用的生成多项式为1+X^3+X^7。要求具有一个RESET端和两个控制端来调整寄存器初值(程序中设定好四种非零初值可选)。-Design a pseudo-random sequence generator, using the generating polynomial 1+ X ^ 3+ X ^ 7. Requires a RESET terminal end and two control registers to adjust the initial valu
pn
- 基于Xilinx的ISE9.0编译的周期为63的m序列-Compiled based on Xilinx' s ISE9.0 63 m sequence of period
m
- 由20位移位寄存器线性反馈产生的m序列的vhdl代码-20-bit shift register linear feedback sequence generated vhdl code m
communications_1
- 用vhdl代码描述的通信系统仿真程序。包括信源(20位m序列),crc编码(采用串行算法),加噪(用22位m序列产生稀疏的1,然后和编码后的数据异或)。-Vhdl code with the simulation program described in the communication system. Including the source (20 m sequence), crc code (using the serial algorithm), noise (with 22 m se