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FirstOrderDigialFiltersforSeond-OrderDigitalPLLs.
- This a short paper discussing three implementations of digital loop filters for phase-locked loops (PLLs) implemented either in digital circuitry or in software. This paper is by no means intended to be a comprehensive theoretical discussion of t
lunwen
- 潘明海 刘英哲 于维双 (论文) 中文摘要： 本文讨论了一种可在FPGA上实现的FFT结构。该结构采用基于流水线结构和快速并行乘法器的蝶形处理器。乘法器采用改进的Booth算法，简化了部分积符号扩展，使用Wallace树结构和4-2压缩器对部分积归约。以8点复点FFT为实例设计相应的控制电路。使用VHDL语言完成设计，并综合到FPGA中。从综合的结果看该结构可在XC4025E-2上以52MHz的时钟高速运行。在此基础上易于扩展为大点数FFT运算结构。 -Pan Mingha
20090903FPGA
- 本文论述并设计实现了一个脱机自由手写体数字识别系统。文中首先对待识别数字的预处理进行了介绍，包括二值化、平滑滤波、规范化、细化等图像处理方法；其次，探讨了如何提取数字字符的结构特征和笔划特征，并详细地描述了知识库的构造方法；最后采用了以知识库为基础的模板匹配识别方法,并以MATLAB作为编程工具实现了具有友好的图形用户界面的自由手写体数字识别系统。实验结果表明，本方法具有较高的识别率，并具有较好的抗噪性能。-In this paper, designed and implemented an o
Realization_of_FPGA_for_LDPC_encoding
- 低密度奇偶校验码(简称LDPC码)是目前距离香农限最近的一种线性纠错码，它的直接编码运算量较大，通常具有码长的二次方复杂度．为此，利用有效的校验矩阵，来降低编码的复杂度，同时研究利用大规模集成电路实现LDPC码的编码．在ISE 8．2软件平台上采用基于FPGA的Verilog HDL语言实现了有效的编码过程，为LDPC码的硬件实现和实际应用提供了依据-Abstract：Low．density parity·check code(LDPC code)is a kind of linear eror
crossroute-R4
- As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstalk has primarily been a concern for ASICs, multi-chip modules, and
Embedded_Remote_Control_System_Based_on_GPRS
- 本课题基于ARM嵌入式硬件平台，以嵌入式Linux为操作系统，设计并实现了一个远程控制系统。该系统主要包括远程控制终端系统、控制服务器系统和受控终端系统三大模块，实现了GSM短消息收发、GPRS数据传输、视频图像采集、蓝牙无线通信、直流电机变速控制和远程终端人机交互等功能。该系统可广泛应用于智能家居、工矿采集和机械生产等远程控制方面。-The remote control system designed and implemented in the paper is based on ARM e
car
- 本文通过数字电路中集成芯片的综合应用，设计出了满足要求的小汽车遥控电路。在电路中，实现了小汽车的前进、后退、左转、右转四个单独功能的控制，在此基础上，实现了三种路径（前后、人字、8字）行驶的自动驾驶控制，并且，设计了速度适中，两档可控的转换电路，最后，电路中实现了暂停功能的控制。-In this paper, an integrated circuit chip digital integrated application designed to meet the requirements of
ss
- REMOVAL OF NOISE FROM ECG (ELECTROCARDIOGRAPHY) BY USING MATLAB. EEG (Electroencephalograph) recording from the scalp has biological artifacts and external artifacts. Biological artifacts, which are generated, can be EMG (Electromyography) sign
cordic
- we propose a low-cost sequential and high performance architecture for the implementation of CORDIC algorithm in two computation modes. It suited for serial operation that performs conversion between polar and rectangular coordinate systems, essentia
synth_fft
- fftprocessing can complete 256 pointsFFT.-Hardware Descr iption Language(HDL)is an advanced electronic designmethod．After HDL was put into use，it has draw great attention and gained popularity．The design used Verilog HDL and Schematic for entry tools
FPGA-Median-Filter
- Digital filtering algorithms are most commonly implemented using general purpose digital signal processing chips for audio applications, or special purpose digital filtering chips and application- specific integrated circuits (ASICs) for higher
Truly-RNG-Based-On-a-D-Scroll-Attractor
- Abstract—In this paper, a novel true random bit generator (TRBG) based on a double-scroll attractor is proposed. The double-scroll attractor is obtained from a simple model which is qualitatively similar to Chua’s circuit. In order to face the
10.1.1.91.4463
- Abstract—Many portable systems deploy operating systems (OS) to support versatile functionality and to manage resources, including power. This paper presents a new approach for using OS to reduce the power consumption of IO devices in teractive
20110301151907
- ：为解决现有视频监控系统中目标检测算法无法应付复杂的室外环境且计算量和存储量较大等问题，将像素从RGB 空间转换到YUV 空间建立基于码本的背景模型，并单独对每个码字中的亮度分量进行高斯建模，提取运动目标的轮廓后，用连通区域算法对图像进行形态 学处理。典型测试序列和ROC 数据的对比实验结果证明该算法是高效和实用的，且易于在DSP 或FPGA 等嵌入式系统上实时实现。-】In order to solve the problems that the existing motion det
VGA_CCD531
- 本文围绕一个包含Nios II软核处理器的可编程片上系统展开数码相机的样机设计。论文首先对样机所要达到的整体功能进行了规划，接下来并行开展了软硬件设计。在硬件方面，充分利用了所使用平台提供的SD卡插槽、键盘、数码管、SRAM等各种硬件资源，并用Verilog HDL硬件描述语言设计了样机系统所需要的VGA接口控制器、CMOS图像传感器接口控制器以及VGA显示存储器；在软件方面，本文基于Nios II软核处理器用C语言实现了SD卡的驱动、FAT文件系统的移植、VGA显视器的驱动以及BMP图片文件的
The-Real-Time-Implementation-of-3D-Sound-System--
- This paper describes a real-time 3D sound system implemented with the use of embedded DSP. We develop a headphone-based new 3D sound algorithm by applying source localization method using HRTF. Localizing 5.1-channel data appropriate loca
3194418washing_machines
- 基于单片机的洗衣机控制，proteus设置本文主要探讨采用Proteus仿真软件,实现全自动洗衣机控制系统硬件、软件的仿真设计和调试运行。本设计采用AT89S52单片机作为控制核心,以洗衣机作为控制对象,采用相应的输入、输出设备,实现对洗衣机整个洗衣过程的多种控制。本文介绍了从方便、快捷的角度出发进行的全自动洗衣机控制方案设计,使用Protues仿真软件进行的硬件电路设计,全自动洗衣机控制系统软件程序的设计,最后在基于硬件原理图的虚拟原型上添加编写好的程序,实现了硬件、软件的实时调试和仿真运行。
1-D-DWT_verilog-code
- Image compression is one of the prominent topics in image processing that plays a very important role in reducing image size for real-time transmission and storage. Many of the standards recommend the use of DWT for image compression. The compu
Dynamic-Noise-Reduction-Algorithm
- n this paper, a new dynamic noise reduction algorithm is proposed based on time-variety filter (TVF), which can be implemented in both time and modified discrete cosine transform (MDCT) domain. In time domain, an IIR filter with changeable ba
approximate-compressor
- implemented Paper is attached. Its on approximate compressor used for multiplication