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fulladder.vhd 一位全加器
adder.vhd 四位全加器
multi4.vhd 四位并行乘法器-fulladder.vhd a full adder adder.vhd four full adder mult i4.vhd four parallel multiplier
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本源码是高速并行乘法器的设计源码,开发软件为MAX+PLUS.输入为两个带符号的二进制数-the source is a high-speed parallel multiplier design source, development of software for MAX PLUS. with the importation of two symbols of binary -
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基于verilog的fir滤波器设计,用的并行结构。在前面基础上加入四级流水(加法器,并行乘法器,乘法结果相加两级),通过验证。-Verilog-based design of fir filter using the parallel architecture. In front of the basis of adding four water (adder, parallel multiplier, multiply the result of the sum of two), throu
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用HDPLD实现的高速并行乘法器,其输入为两个带符号位的4位二进制数- HDPLD implementation with high-speed parallel multiplier, the input symbols with two 4-bit binary number
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串并FIR滤波器设计:并行FIR滤波器具有速度快、容易设计的特点,但是要占用大量的资源。在多阶数的亚高频系统设计中,使用并行结构并不合算,但亚高频系统需要较高的处理速度,而串行架构往往达不到要求,因此,结合串并这两种设计方法的长处,在使用较少的硬件资源的同时实现了较高的处理速度,这里说明一种65阶八路并行、支路串行FIR滤波器的设计(实际使用了1个乘法器,8个乘累加器,一个累加器)。-String and FIR filter design: parallel FIR filter with a
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潘明海 刘英哲 于维双 (论文)
中文摘要:
本文讨论了一种可在FPGA上实现的FFT结构。该结构采用基于流水线结构和快速并行乘法器的蝶形处理器。乘法器采用改进的Booth算法,简化了部分积符号扩展,使用Wallace树结构和4-2压缩器对部分积归约。以8点复点FFT为实例设计相应的控制电路。使用VHDL语言完成设计,并综合到FPGA中。从综合的结果看该结构可在XC4025E-2上以52MHz的时钟高速运行。在此基础上易于扩展为大点数FFT运算结构。
-Pan Mingha
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This project is "digital serial multiplier". this proh=ject is used to multiply the serial data with parallel data. the source code is writtenby using vhdl.
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介绍了一种64位子字并行乘法器的设计。根据不同的操作模式可以完成普通模式操作即64bit*64bit乘法操作,又可完成子字并行操作模式,即4个16bit*16bit乘法操作。-Introduced a 64-seat word parallel multiplier design. Depending on the operating mode Normal mode operation can be done that 64bit* 64bit multiplication operation
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利用VerilogHDL语言编写的各种各样的乘法器,比如并列乘法器,省时乘法器等-VerilogHDL language using a variety of multipliers, such as parallel multipliers, multiplier and other time-saving
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vhdl code for a 32 bit parallel multiplier
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四位并行乘法器的VHDL源代码,已通过验证,可以使用-Four parallel multiplier VHDL source code has been validated, you can use
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RobustVerilog generic FIR filter
In order to create the Verilog design use the run.sh scr ipt in the run directory (notice that the run scr ipts calls the robust binary (RobustVerilog parser)).
The filter can be built according to 3 differe
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We present elliptic curve cryptography (ECC) coprocessor,
which is dual-field processor with projective
coordinator. We have implemented architecture for scalar
multiplication, which is key operation in elliptic curve
cryptography. Our coproc
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简单16位并行乘法器的Verilog程序-16 parallel multiplier Verilog program
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16位并行乘法器源代码,booth2编码,二进制树拓扑结构-16bits parallel multiplier source code
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parallel pipeline reconfigurable multiplier
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16位并行乘法器,
由四个4位乘法器组成-16-bit parallel multiplier, consisting of four four multipliers
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基于FPGA的32阶FIR数字滤波器设计 源程序。设计使用了并行乘法器,运行速度更快,占用内存更小,延迟更小。
-32 order FIR digital filter based on FPGA design source program. Design USES parallel multiplier, faster and less memory, less delay.
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this a 8-bit Multiplier using 3 stages. after reset the 8 bit operands are loaded and the serial-parallel multiplication takes place.-this is a 8-bit Multiplier using 3 stages. after reset the 8 bit operands are loaded and the serial-parallel multipl
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Multiplication is performed in three stages. After reset, the 8-bit operands are “loaded” and the product register is set to zero. In the second stage, s1, the actual serial-parallel multiplication takes place. In the third step, s2, the product is t
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