搜索资源列表
数字边沿鉴相器
- 数字边沿鉴相器 verilog源程序 -figures for 2500 phase-2500 verilog source digital phase detector verilog source
C51-phasic-detector
- C51 实现的相位检测，带PROTEUS仿真-C51 implementation phase detection, with PROTEUS simulation
costas的verilog程序
- costas的verilog程序，包含乘法器，DDS，鉴相器，环路滤波器等模块-costas the verilog program, including multipliers, DDS, phase detector, loop filter modules
dpll
- 基于Verilog的数字锁相环。包括三个模块，数字鉴相器DPD、数字环路滤波器DLF、数控振荡器 DCO三部分构成-Verilog-based digital PLL. Consists of three modules, the digital phase detector DPD, digital loop filter DLF, digitally controlled oscillator DCO three parts
9700F
- protel99图 电机相位检测板应用于电机的转速检测和相位检测-Figure protel99 board phase detector used in electric motor speed detection and phase detection
PLL
- PPL讲义，关于鉴相器方面的技术资料，对于用单片机编程有好处。-PPL notes, phase detector on the technical information, good use of single-chip programming.
ADF4157
- ADF4157是ADI公司出品的一款锁相环芯片，它含有一个鉴相器，一个电子泵，一个sigma delta 分频器-ADI Corporation ADF4157 is a production of the chip phase-locked loop, which contains a phase detector, an electronic pump, a sigma delta prescaler
tongxin
- 自己做的测频测相器（硬件使用EPM240采样计数mega16取数和控制），此为EPM240的程序，使用quartus编程，主要包含两个接近20位的计数器。-This is the frequency and phase detector (hardware using EPM240 sampling and counting, mega16 take the number and control), this is EPM240 procedures, using quartus program
avr
- 自己做的测频测相器（硬件使用EPM240采样计数mega16取数和控制），此为Emega16的程序，使用ICCAVR编程，主要包含测频和测相的计数值的处理，和LCD12864的显示-This is frequency and phase detector(hardware using EPM240 sample count mega16 take the number and control), this is Emega16 procedures, the use of ICCAVR prog
pll
- DPLL由 鉴相器、 模K加减计数器、脉冲加减电路、同步建立侦察电路、模N分频器构成. 整个系统的中心频率(即signal_in和signal_out的码速率的2倍)为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低. -DPLL by the phase detector, K addition and subtraction counter mode, pulse subtraction circuit, sy
jianxiang
- 基于ISE的鉴频、鉴相器，开发板：xilinx公司spartan 3E 500.精确度1hz,1度。完全正确。-Based on ISE' s Kam-frequency phase detector, development board: xilinx company spartan 3E 500. Precision 1hz, 1 degree. Entirely correct.
code
- it is the collection of the modules involved inthe design of digital fm.the code coves the key components like numerically controlled oscillator, loop filter, fir filter ,phase detector along with the complete cicuit implementation of the digital fm
Quartus
- Quartus的鉴相器硬件电路设计 Quartus的鉴相器硬件电路设计 -Quartus the hardware design phase detector phase Quartus' s Quartus hardware circuit design of hardware circuit design phase
DPLLdesign
- 数字锁相环频率合成器的设计，数字鉴相器，数字滤波器，数控振荡器，反馈分频器-Digital PLL frequency synthesizer, digital phase detector, digital filter, digital control oscillator, the feedback divider
VPD__using_FFe
- verilog开发一种种基于fpga的鉴相器模块 -the verilog development of all kinds based on fpga phase detector module
dpll1600e
- 数字锁相环的设计，包括鉴相器，环路滤波器，spi口输出，分频器的源代码-Digital phase-locked loop design source code, including the phase detector, loop filter, spi port output divider
DCO_ST
- 单相数字锁相环 鉴相器 环路滤波器 数控振荡器-Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
DPLL_TEST
- 单相数字锁相环 鉴相器 环路滤波器 数控振荡器-Single-phase digital phase-locked loop phase detector loop filter numerically controlled oscillator
dpll2
- 数字锁相环的vdhl实现，鉴相器，计数器，压控振荡器，和分频器-Vdhl DPLL implementation, the phase detector, a counter, a voltage controlled oscillator, and a frequency divider
dpll
- 用verilog编写的全数字锁相环，包括鉴相器，模K计数器，加减脉冲模块和分频模块，都经过验证-verilog based digital phase lock loop design, including phase detector,mode K counter, increment/decrement counter and frequency divider