搜索资源列表
gong_fen_baohu
- 负载输出L,R，都应对地是交流，经R3，R4,C2,C3，入地，交流对地短路，没有直流信号；若有一路含有直流成分，将在电阻电容节点产生或正或负的电压，经二极管桥，整成直流，当电压超过二极管正向电压和Q1导通电压时，Q1导通，Q2，Q3截止，继电器释放，起到某一通道不正常时保护。 此电路还有开机延时保护：开机，电压经R2向C4充电，电压慢慢上升，电压达到D8，Q2，Q3导通电压时，继电器吸合。达到延时接通负载作用-L, R, should all is AC load output by R3
usb1029
- 实现FPGA对Cypress公司的68013A款的USB芯片应用于SLAVEFIFO的读操作，使用verilog语言编写，Q2开发环境。-FPGA to realize the company s 68013A paragraph Cypress USB chip used SLAVEFIFO read operation, using verilog language, Q2 development environment.
Cyclone4_SD_Card_Audio_Player
- 基于cyclone4 FPGA芯片的音频播放器完成项目工程，包括SOPC项目代码，以及SD卡读取模块Verilog IP，以及完整的Q2下项目工程。-Cyclone4 FPGA chip based audio player to complete the project works, including the SOPC project code, and SD card reader module IP, as well as complete Q2 next project.
Lab14_count3a
- 8分频器的设计与实现.8分频器的真值表，其最高位q2的输出就是对输入信号的8分频。本实验中用Verilog来实现。-Design and implementation of.8 8 frequency divider divider of the truth table, output the highest bit Q2 is the input signal frequency of 8. Use Verilog to achieve in this experiment.
dds
- 使用FPGA产生DDS信号发生器，方便移植，适合新手学习，开发环境Q2-Use FPGA generate DDS signal generator, easy migration, suitable for novices to learn, develop environment Q2
moore
- FPGA实现moore状态机，适合新手学习，开发环境Q2-FPGA implementation moore state machine, suitable for novice learning, development environment Q2
Q2.tar
- vereilog design files for beginer