搜索资源列表
pcm
- 该程序设计了一个产生PCM码流时序信号的模块，他包括输入端CLK，SET及输出端Q1,Q2,Q3-the program have designed a PCM signal timing modules, including the CLK input, and output SET Q1, Q2 and Q3
串口verilog源代码
- 串口UARTverilog源代码。包括控制模块、收、发模块。程序全，功能简洁，包含Q2工程
key44.rar
- fpga_4X4矩阵键盘程序，有消抖，下载后可直接使用，Q2中综合已通过 ,Matrix keyboard fpga_4X4 procedures Buffeting extinction, can be used directly after downloading, Q2 integrated through
divider
- 基于Verilog的除法器设计，可以直接在Q2里面运行哦~-Verilog-based design of the divider, which can be run directly in Q2 Oh ~
dds_1024
- fpga实现DDS，1024个点，已通过Q2综合，绝对好用-fpga achieve DDS, 1024 points have been integrated through Q2, the absolute ease of use
key_8
- FPGA单排键盘程序—已消抖，下载后可直接使用，Q2中综合已通过，基于cyclone-FPGA single-row keyboard program- has been shaking extinction, can be used directly after downloading, Q2 integrated through
jishu10
- FPGA——1位10进制计数程序，可用原理图输入法拓展n位，下载后可直接使用，Q2中综合已通过，基于cyclone-FPGA- 1 station 10 hexadecimal counting procedures, schematics can be used to expand n-bit input, can be used directly after downloading, Q2 has passed comprehensive, based on the cyclone
8led
- verilog HDL上的8段LED跑马灯效果，Q2开发的希望对各位初学者有用-verilog HDL on the effect of 8-segment LED Marquee, Q2 development you want to be useful for beginners
chuanbin
- 对信号进行串并转换，使其分成I,Q2路输出信号 -String and convert the signal to make it into I, Q2 output signal
ask
- 这个是基本q2和dspbuilder的ask实现，是做实验的好参考资料。-This is the basic realization of q2 and dspbuilder the ask is a good reference experiment.
Verilog-Niosii-TLC1549
- niosii的一个完整的工程 Q2 软件是9.1版本，里面做了一个TLC1549的AD转换串转并的模块-niosii project with a TLC1549 module
QuartusII-detailed-crack-video
- QuartusII详细破解视频。对安装Q2有帮助。-QuartusII detailed crack video. Of installation Q2.
dpsk_3rd
- 2DPSK调制与解调。学生实验使用，包括信号源模块、时钟源生成模块、信号调制模块，信号解调模块。 其中包含了边沿触发下的阻塞语句。 编译环境：Q2 11.0，编译语言：verilog，仿真软件：moelsim altera -2DPSK modulation and demodulation. The student experiments, including the source module clock source generation module, signal modu
usb1029
- 实现FPGA对Cypress公司的68013A款的USB芯片应用于SLAVEFIFO的读操作，使用verilog语言编写，Q2开发环境。-FPGA to realize the company s 68013A paragraph Cypress USB chip used SLAVEFIFO read operation, using verilog language, Q2 development environment.
Cyclone4_SD_Card_Audio_Player
- 基于cyclone4 FPGA芯片的音频播放器完成项目工程，包括SOPC项目代码，以及SD卡读取模块Verilog IP，以及完整的Q2下项目工程。-Cyclone4 FPGA chip based audio player to complete the project works, including the SOPC project code, and SD card reader module IP, as well as complete Q2 next project.
Lab14_count3a
- 8分频器的设计与实现.8分频器的真值表，其最高位q2的输出就是对输入信号的8分频。本实验中用Verilog来实现。-Design and implementation of.8 8 frequency divider divider of the truth table, output the highest bit Q2 is the input signal frequency of 8. Use Verilog to achieve in this experiment.
dds
- 使用FPGA产生DDS信号发生器，方便移植，适合新手学习，开发环境Q2-Use FPGA generate DDS signal generator, easy migration, suitable for novices to learn, develop environment Q2
moore
- FPGA实现moore状态机，适合新手学习，开发环境Q2-FPGA implementation moore state machine, suitable for novice learning, development environment Q2
Q2.tar
- vereilog design files for beginer