搜索资源列表
VHDLbaseddesignofmusicplayer
- 在EDA开发工具Quartus II 6.0平台上，采用VHDL语言层次化和模块化的设计方法，通过音符编码的设计思想，预先定制乐曲，实现动态显示乐曲演奏电路的设计，并在此基础上，基于同一原理，使此电路同时具备了简易电子琴的功能，使基于CPLD/FPGA芯片的乐曲播放数字电路得到了更好的优化，提高了设计的灵活性和可扩展性。- Based on the QuartusII-the EDA development tool, this design has adopted the method of
vgaroundn
- VHDL语言在QUARTUS II环境下控制VGA显示器显示彩色小球的程序-VHDL language QUARTUS II VGA display under control of the ball in the process of color
VerilogProjects
- 在quartus II环境下用Verilog实现了8255, 8253, 8259, 8250, DAC0832, ADC0809等微机接口芯片，硬件设计实验课的作品，有些芯片的功能有所简化，但最基本的功能已实现，有完整的时序仿真波形-In quartus II environment achieved with Verilog 8255, 8253, 8259, 8250, DAC0832, ADC0809 and other computer interface chip, hardware
krtlcd
- 基于FPGA的液晶显示驱动知识研究，可在quartus II环境下运行-FPGA-based knowledge of liquid crystal display driver can be run in quartus II environment
Spread-Spectrum-Receiver-code
- 基于FPGA的扩频接收机（直扩）vhdl编写的，最好在quartus环境运行。-FPGA-based spread spectrum receiver (DS) vhdl prepared, the best environment to run in quartus.
0101
- Quartus II 除法器，用VHDL语言编写的.除法器。-Divider using VHDL language. Divider
asi_test_1229OK
- 基于quartus的cycloneii的小程序-Quartus the cycloneii on small programs
Traffic_Light
- 根据城市的十字路口各部门和在不同时间的交通流量，智能交通灯控制方案，并给出基于VHDL语言，采用层次结构设计的QuartusⅡ模拟思想。-According to the different branches of city’s intersections and the traffic flow at different times, the program of intelligent traffic light controller based on VHDL is given and s
DDS_Set
- AD9852，DDS芯片接收数据逻辑。（Verilog语言）-AD9852, DDS chips receive data logic. (Verilog language)
stopwatch
- verilog 秒表程序 用quartus 编写-Verilog stopwatch ............................................................................................
EDA4
- 1、熟悉Quartus软件的使用及设计流程。 2、掌握利用宏模块设计方法，即使用端口和参数定义生成宏功能模块。 3、掌握正弦信号产生的原理和方法。-1, familiar with the Quartus software use and design flow. 2, using macro control module design method, which uses port and parameter definition of the macro function modu
SDRAMtest
- 使用quartus软件打开 内含sdram测试文件代码语言为verilog 备注清晰，适合初学者-Quartus software using open source test file containing sdram verilog Remarks clear language, suitable for beginners
DDS_100325(13)_success
- QUARTUS II环境下VHDL语言编写DDS程序，双数字信号输出，一为正弦波幅值输出，一正弦波差值信号。时钟2^21HZ，带24bits频率控制字。-QUARTUS II environment, VHDL language DDS program, two digital signal output, an amplitude for the sine wave output, a sine wave difference signal. Clock 2 ^ 21HZ, with 24bi
190.7_Freq_divider
- QUARTUS II环境下VHDL编写的小数点分频器程序，实现190.7分频，可以将50MHz时钟频率分频成约等于2^21Hz频率，方便特殊情况下的运算-QUARTUS II, prepared under the decimal divider VHDL program to achieve 190.7 frequency, you can divide into a 50MHz clock frequency is about equal to 2 ^ 21Hz frequency, eas
Verilogexamples
- Verilog初学编程实例，包括源程序及QuartusⅡ仿真结果，适合初学者了解学习-Verilog beginner programming examples, including source code and Quartus Ⅱ simulation results, suitable for beginners to understand the learning
altera_de2_vhdl
- Tutorial of VHDL with Altera DE2 board: quartus II and DE2 board The target do the BCD sum of input data coded with the switches and display the result on 7 segment display
total_game
- 用VHDL编写的小游戏，采用FPGA开发板，外接键盘和数码管可实现。 Quartus II上运行通过，并用FPGA实现。-failed to translate
singet
- quartus II环境下正选波发生器源代码 下载后可通过内嵌逻辑分析仪观测波形-quartus II environment, elections wave generator is download the source code can be embedded logic analyzer waveform observation
quartus_ii_tutorial_hierarchical
- quartus guide book for verilog
quartus_ii_tutorial
- quartus- II tutorial