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muxfile
- 基于FPGA设计ADC0809采样控制器原代码-FPGA-based design ADC0809 Sampling Controller source
c822.rar
- 关于FPGA的一个设计，用FPGA来实现数字示波器，采样时钟为250M,On a FPGA design, FPGA to realize digital oscilloscope, the sampling clock for the 250M
sin.rar
- 用Verilog语言在FPGA内实现一256个采样点的正弦波，已尝试，挺好用的~~~,Verilog language used in the FPGA to achieve one of the 256 sampling points sine wave, I have already tried it, very useful~ ~ ~
bridge
- FPGA和A/D转换芯片ad7862的IP，可实现4路数据的采样和读取。 用verilog实现的-FPGA and the A/D conversion chip ad7862' s IP, can achieve 4-way data sampling and reading. Achieved with verilog
ADconverter
- 基于FPGA的A_D转换采样控制模块的设计-A Design of the A/D Convertion Sampling Control Module Based on FPGA
caiyang
- 种用FPGA 实现对高速A/ D 转换芯片的控制电路,系统以MAX125 为例,详细介绍了含有FIFO 存储器的A/ D 采样控制电路的设计方法,并给出了A/D 采样控制电路的V HDL 源程序和整个采样存储的顶层电路原理图.-Species with FPGA to achieve high-speed A/D conversion chip control circuit, the system as an example to MAX125 details FIFO memory cont
DigitalOscilloscope
- 本数字示波器以单片机和FPGA为核心，对采样方式的选择和等效采样技术的实现进行了重点设计，使作品不仅具有实时采样方式，而且采用随机等效采样技术实现了利用实时采样速率为1MHz的ADC进行最大200MHz的等效采样。同时系统还具有可测2mV小信号、波形存储回放、测频、触发沿选择、校准信号输出等功能。-The digital oscilloscope and a single-chip FPGA as the core, the choice of the sampling methods and
DDS
- 本代码可以用于产生正余弦信号波形，利用FPGA内部的ROM放置一个正余弦采样点的数据表格，通过循环取址的方法，实现波形连续输出。-This code can be used to generate positive cosine signal waveforms, using FPGA' s internal ROM to place a sampling point is the cosine of the data tables, the circulation method of t
2345676588FPGAxiebofenxi
- 本文给出一种基于FPGA的新型谐波检测系统的设计方案。在该方案中，采用FPGA实现快速的FFT运算，采用数字锁相环来同步被测信号，以减小由非同步采样所产生的误差并给出实现的设计实现。数字锁相环和FFT算法用VHDL语言设计实现，该方案能提高谐波分析的精度以及响应速度,同时大大地精简了硬件电路, 系统升级非常方便。-This paper presents a new FPGA-based harmonic detection system design. In the scheme, using
shishi
- 基于FPGA的实时采样系统设计！双口ram典型应用！-FPGA-based real-time sampling system!
equivalent_sample
- 基于FPGA的等效采样系统设计，包含状态机设计，双口ram使用方法，分频设计等-FPGA-based equivalent sampling system design, including the state machine design, dual-port ram usage, frequency design
adc0809
- 利用FPGA控制ADC0809采样电压，并通过数码管显示电压数值-ADC0809 FPGA control by sampling the voltage and the voltage value through the digital display
PLD-LOGIC_SPWM
- 电子设计竞赛中获二等奖，在FPGA中实现的两路自然采样SPWM，原理图输入法设计，1024*八位正弦查找表，带FSK和ASK调制功能，频率范围8KHz~12KHz.-Electronic Design Competition second prize in the FPGA to achieve the two natural sampling SPWM, schematic design input, 1024* eight sine look-up table, with FSK and A
adc
- 设计ADC控制器，Verilog代码.利用有限状态机设计方法在FPGA上设计ADC0809的接口控制器，采样结果送到数码管显示出来。-ADC controller design, Verilog code using finite state machine design in the FPGA design ADC0809 interface controller, the sampling results to the digital display.
state_FPGA
- 基于FPGA的状态机，应用于高速A/D采样上，通过测试-FPGA-based state machine, used in high-speed A / D sampling, the test
my_adc1
- 020单片机ADC1采样程序；额外功能：main中主要实现与FPGA并口通信，总体实现FFT,不过FPGA部分没有上传，因此能实现的是ADC1采样。-020 SCM ADC1 sampling procedures additional features: main key to achieve in parallel with the FPGA communication, achieving an overall FFT, but the FPGA portion not uploaded
dso
- 基于fpga的简易数字存储示波器设计，包含采样，检测触发，波形存储等模块功能-Fpga-based design of simple digital storage oscilloscope, including sampling, testing the trigger, waveform storage module functions
ADSample_FPGA
- 开发环境为QuartusII。这是AD采样的verilog代码部分，在FPGA上硬件实现AD采样的一部分功能-Development environment for the QuartusII. This is the verilog code for part of the AD sample, the FPGA hardware on the part of the function AD sampling
yinpinfangda
- 采用基于FPGA的频域加窗与反傅立叶变换的数字幅频均衡功 率放大器:此方案采用高速FPGA，以及配套的高速AD、DA 对信号进行采样，傅 立叶变换，在频域上对信号进行加窗操作，然后通过傅立叶反变换将波形还原。 以得到需要的频谱幅度。-FPGA-based frequency domain using the windowed Fourier transform with the number of pieces of anti-band equalizer amplifier: Th
ADC9481
- 利用FPGA对AD9481进行采样，亲测有用(Sampling ad9481 with FPGA)