搜索资源列表
SDRAM1
- 这是一个控制sdram的程序，用verilog编写的-This is a control program sdram, prepared with verilog
project1_supplemental1
- these are projects based on verilog like memory control, sdram control etc-these are projects based on verilog like memory control, sdram control etc..
sdr_test
- sdram读写测试程序，带modsim仿真文件-verilog code of reading and writing of sdram, with modsim simulation test file.
sdram_control
- FPGA 用verilog控制sdram读写-FPGA control with verilog sdram read and write
SDRAM_TEST
- 用Verilog硬件描述语言驱动SDRAM，内有完整可实现源代码，且还有现象说明-With the Verilog hardware descr iption language driven SDRAM, can be realized within the complete source code, and there is the phenomenon described
tut_DE1_sdram_verilog
- a complete tutorial on the sdram a verilog code
sdram_vhdl
- DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的。-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good.
Source
- I2C 控制器的 Verilog源程序以及I2C规范说明-The I2C bus provides a simple two-wire means of communication. This protocol is used in many applications.SDRAM modules implement a serial EEPROM that supports the I2C protocol. This is used so that a micro
FPGA_Project_Files
- 基于sdram的pci设计，包含整个工程，verilog编写-The design is base on sdram, contain a whole project ,using the verilog language.
memory-controller
- 存储控制器，包括CPUside，接口，MEMORY side三个部分，使用verilog语言-This represents the "memory controller" It runs with the assumption that it is being connected to PC100 SDRAM.
FSM
- FPGA学习资料，新手入门资料,VERILOG- Micron SDRAM DDR2 Simulation model Verilog
sdram_mdl
- verilog实现SDRAM控制器，quartus工程-verilog SDRAM controller, quartus project
altera_sdram
- 基于quartus平台的sdram控制器设计（verilog 源码）-Based on the the quartus platform, the SDRAM controller design (Verilog source code)
Sdram_Control_4Port
- 使用verilog HDL写的sdram(SDR)的控制器源代码，具有很好的可移植性，试验的例子已经通过QuartusII 9.0编译通过，可以运行在cycloneII上-Controller source code using verilog HDL written in the sdram (SDR), has good portability, test examples via the QuartusII 9.0 compiler, you can run in cycloneII
Design-Of-DDR-SDRAM-Using-Verilog-HDL
- implementation of ddrsdram
sdram_mdl
- SDRAM的FPGA 工程。用Verilog编写。器件型号为K4S641632，经过实验板验证，绝对可用。-SDRAM FPGA project. Written in Verilog. Device model K4S641632, after the experimental board, absolutely available.
sdram_mdl
- FPGA控制SDRAM的工程，是用Verilog写的，很好用-FPGA to control the SDRAM project is written in Verilog, easy to use
sdram_me
- 用verilog代码控制sdram,sdram_module是顶层模块。控制8M x 16bits x4Banks sdram. -use verilog program to control the sdram
DE2_70_NIOS_10_flash
- 首先将此Verilog程序下载到DE2-70开发板上后，然后用NiosII软件将任何文件的二进制数据写入到ssram或者sdram等存储器重去，并可以指定起始地址。-First program this Verilog downloaded to the DE2-70 development board, and then the use NiosII software binary data of any file written to memory such as ssram or sdra
LL
- verilog语言描述的SDRAM程序代码。-verilog language to describe the the SDRAM procedure code.