搜索资源列表
ram
- 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ens
pn_generator.rar
- FPGA实现pn发生器，Verilog代码实现，另带modlesim的仿真测试文件，很有价值。,FPGA realization of pn generator, Verilog code, and the other with the simulation test modlesim documents of great value.
test74hc595
- 74hc595仿真的测试，值得大家去看看，对74hc595更好的运用。-74hc595 simulation test, worth to see better use of 74hc595.
chuankou
- 利用汇编语言编写的串口通信程序，可发送数字并显示在接收端的数码管上，用PROTEUS7仿真，测试通过，运行良好-Written in assembly language using serial communication program, the number can be sent and displayed at the receiving end of the digital control, and with the PROTEUS7 simulation, test, run goo
dds
- verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
atmega8-6ADC
- AVR系列ATmega8单片机制作的6路ADC同时检测6个电压程序，检测结果使用数码管，使用ICCAVR编写，附Proteus仿真文件。-AVR Series ATmega8 microcontroller produced use 6-channel simultaneous detection of six voltage ADC program, test results of the use of digital control, the use of ICCAVR write, wit
TLC5510_IIPRAM1
- FPGA控制双口RAM、实现TLC5510采样控制双口RAM读写！QUARTUS II8.0平台仿真验证通过，并在硬件上运行通过测试！-FPGA control of dual-port RAM, the realization of sampled-data control TLC5510 dual-port RAM read and write! QUARTUS II8.0 platform through simulation and hardware to run through the
pic-i2c-master-test
- PIC单片机I2C通信主模式，内涵Proteus仿真内容-PIC MCU I2C master mode communications, meaning the content of Proteus simulation
1602lcd
- 51单片机1602液晶可调时钟通过了proteusfa仿真测试-51 Single-chip LCD 1602 adopted proteusfa adjustable clock simulation test
FPGA_jiaocheng_yu_shiyan
- 最重要的是七个从简单到复杂的实验，包括：基础实验一_FPGA_LED 基础实验二_seg7实验以及仿真 基础实验三_SOPC_LED 基础实验四_Flash烧写 基础实验五_定时器实验 基础实验六_按键以及PIO口中断实验 实验七_网卡使用 ，这些实验室用到了SOPC BUILDER 与NOIS ii ,使用Verilog 编写，有实验板和没有实验板的都可以用来学习。 其次还包括： FPGA开发板各存储器之间的联系、 多处理器文档 、 USB_UART等文档，很好用的文档，您下了相信不会后悔！-
TranslateToUTOPIA
- VHDL写一个转换到utopia接口的转换源程序.可以进行utopia接口的仿真试验-VHDL to write a converter to convert source utopia interface. Can utopia interface simulation test
Test
- Proteus based avr simulation
A_bit_serial_data_transmitter
- 比特序列传送模块 把输入的八位比特数据 做循环后每个比特输出 详细请看英文描述-• To create Verilog-HDL modules written in the RTL style appropriate for both simulation and synthesis, for the various component parts of an Asynchronous Serial Data Transmitter. • To verify th
FPGAbasedPCIinterfacedesignanditssimulation
- 基于FPGA的PCI接口设计的源代码以及其仿真测试文件-FPGA-based PCI interface design of the source code and its simulation test file
RD1011_rev01.2
- 采用VHDL实现的UART硬件模块，该模块包括了modem的硬件实现，已经仿真测试代码，顶层模块可以采用VHDL或verilog实现，便于嵌入到自己的设计之中。文档中附有详细的使用说明和注释。-Achieved using VHDL hardware UART module, the module includes the hardware modem has simulation test code modules can be used top-level VHDL or verilog t
scen-500-test
- ns2 tool simulation senario
test
- 比较两个数大小的源程序，使用Verilog编写，而且包含了测试代码部分，可用modelsim仿真得到波形-Comparison of two numbers the size of source, using Verilog write, but also contains some test code that can be used to be waveform simulation modelsim
FIR
- FIR滤波器的VHDL源代码及测试文件，已通过编译仿真，绝对正确。-FIR filter VHDL source code and test files, has passed the compiled simulation, absolutely correct.
M16_LCD1602
- 本程序实现M16的LCD602显示以及在Protues下的仿真，测试成功-This program to achieve the LCD602 display M16 and Protues under the simulation, test success
1602LcdDrive
- 实现1602字符显示，时序良好运行精确已仿真测试通过-Achieve the 1602 character display, timing accuracy has been a good run through the simulation test