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(PWM)
- 方波发生器程序。AVR单片机程序。MEGA16-Square-wave generator procedures. AVR Singlechip procedures. MEGA16
pre_norm_sqrt
- 一种用VHDL语言描述的浮点平方根前规格化的源代码编程-VHDL language used to describe a floating-point square root of the source code before the standardized programming
square
- 按下16个矩阵键盘依次在数码管上显示1-16的平方。如按下第一个显示1，第二个显示4... 在keil下编程，用proteus仿真 -Press the keyboard matrix followed by 16 in the digital tube display the square of 1-16. Touching the first show that 1, the second show the next 4 ... in keil programming, sim
square
- 51单片机实现方波信号可调输出，显示输出频率和周期，按键设定方波周期，显示模块为20S207DA4-51 single-chip implementation adjustable output square wave signal, showing the output frequency and the cycle of square-wave cycle button settings, display module for 20S207DA4
leastsquarea
- least square estimation of system identification
signal
- verilog写的串口控制信号发生器，能通过用串口控制产生正弦波方波等信号-written in verilog serial control signal generator, can be generated using serial control, such as sine wave square wave signals
sq-rt
- ARM assembly, code warrior, routine for calculating square root of an input number
sqrt
- This zip file contains the verilog source code for square root calculation and its test bench
lms2
- this algorithm based on least mean square -this is algorithm based on least mean square
SIGNAL_GEN
- 利用EDA的VHDL硬件描述语言设计的函数信号发生器，可以产生递增、递减斜波，三角波，阶梯波，正弦波，方波-The use of EDA, VHDL hardware descr iption language design function of the signal generator can generate increased progressively decreasing ramp, triangle wave, step-wave, sine wave, square wave
square-root
- Verilog硬件描述语言能够用软件语言的的方式描述硬件特性，并可用仿真方式完成电路的调试.本文介绍了基于EasyFPGA030的开平方运算器的设计，详细说明了运用verilog语言的设计过程与实现成果。-Verilog hardware descr iption language（HDL）specializes in describing hardware in the way of software language, and complete circuit simulation avai
square
- This a verilog code for the generation of a square wave-This is a verilog code for the generation of a square wave..
S6_VGA_change
- 程序可以在VGA显示器上以800x600分辨率显示方波示例和字母示例-Program can display in VGA resolution display with 800x600 square wave sample and sample letters
HDLImplementationoftheVariableStepSize
- proposes a Verilog implementation of the Normalized Least Mean Square (NLMS) adaptive algorithm, having a variable step size. The envisaged application is the identification of an unknown system. First the convergence of derived LMS algorithm
wave_finish
- 基于quartus2的信号发生器，可产生正弦，三角，方波-Based quartus2 signal generator can produce sine, triangle, square wave. .
100-2000Hz-square-wave
- C8051F410单片机使用定时器0产生方波-C8051F410 microcontroller timer 0 produce square-wave use
LinPF_RLS
- VHDL code for linear prediction filter based on RLS (recursive least square). Filter order is set to 4, bit precision set to 12 bits for input and output. Signals are complex signals.
square
- This program uses the 68681 timer to create a 2 Hz square wave on OP3
square-wave(1-9ms)
- 基于C51单片机用C语音实现方波，周期可在1-9ms之间调节-C51 Microcontroller based voice to achieve a square wave with a C, the cycle can be adjusted between 1-9ms
A-VHDL-Function-for-finding-SQUARE-ROOT
- vhdl coding for square root-vhdl coding for square root...