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  1. systolic

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  2. 脉动乘法器:一个GF(2m)域上的Digit-Serial 脉动结构(Systolic)的乘法器
  3. 所属分类:VHDL编程

    • 发布日期:2008-10-13
    • 文件大小:2560403
    • 提供者:chenyi
  1. Systolic-Algorithm-for-B-Spline-Patch-Generation.

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  2. Systolic Algorithm for B-Spline Patch Generation
  3. 所属分类:SCM

    • 发布日期:2017-03-30
    • 文件大小:726041
    • 提供者:eric
  1. Copy-of-Systolic-Architecture-to-convert-colour-t

    0下载:
  2. the paper presents efficient colour conversion algorithm for fpga implementations
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:294819
    • 提供者:arun scaria
  1. Systolic_Array

    0下载:
  2. Multiplier using systolic array
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-09
    • 文件大小:101885
    • 提供者:Ali
  1. SDRAM-USING

    0下载:
  2. Field programmable gate arrays (FPGAs) are emerging in many areas of high performance computing, either as tailor made signal processor, embedded algorithm implementation, systolic array, software accelerator or application specific architecture. FPG
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-12
    • 文件大小:2638726
    • 提供者:javad
  1. TABLOO

    0下载:
  2. Field programmable gate arrays (FPGAs) are emerging in many areas of high performance computing, either as tailor made signal processor, embedded algorithm implementation, systolic array, software accelerator or application specific architecture. FPG
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-31
    • 文件大小:248558
    • 提供者:javad
  1. XILINX-JTAG-PROGRAMER

    0下载:
  2. Field programmable gate arrays (FPGAs) are emerging in many areas of high performance computing, either as tailor made signal processor, embedded algorithm implementation, systolic array, software accelerator or application specific architecture. FPG
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:19497
    • 提供者:javad
  1. behavioral

    0下载:
  2. This is a code for systolic multiplier,it can be modified for more lenght in data input
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-07
    • 文件大小:365903
    • 提供者:andres calderon
  1. systolic

    2下载:
  2. 实现QR_RLS算法,基于fpga 的非线性功放的dpd实现-realize QR_RLS
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-28
    • 文件大小:24630
    • 提供者:wangding
  1. systolic--matrix-inversion

    0下载:
  2. DSP算法架构及设计,内容为基于systolic的上三角矩阵求逆电路的实现,里面有详尽的MATLAB/SIMULINK 仿真模型,及HDL代码和在modelsim中的仿真程序,非常不错的。-Architecture and design of DSP algorithms, based on systolic upper triangular matrix inverse circuit to achieve detailed MATLAB/SIMULINK model and the HDL
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-10
    • 文件大小:1387193
    • 提供者:
  1. Homework4

    0下载:
  2. 4x4矩阵乘法,使用pipeline结构,可以在AutoESL中综合出Verilog,并在System Generator中测试通过。-Matrix multification in systolic way for AutoESL synthesis
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-12-07
    • 文件大小:2210759
    • 提供者:liu
  1. systolic_mul_D8_M193

    0下载:
  2. 193位8段的GF(2m)域上的Digit-Serial 脉动结构(Systolic)的乘法器-a 193bit GF(2m) Ditital-Serial Systolic Multiplier
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:63381
    • 提供者:yefeng
  1. matrix-inversion

    2下载:
  2. 基于Systolic的上三角矩阵求逆的实现,含有详细的verilog代码,并给出详细的注释-upper triangular matrix inversion
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-29
    • 文件大小:136084
    • 提供者:孙永林
  1. Copie de Rapport du

    1下载:
  2. the classification of cardiac signals, the methods described in the literature to classify S1 and S2, are based on temporal criteria (duration of systole and diastole) which will no longer be valid in several pathological cases such as tachycardia st
  3. 所属分类:嵌入式/单片机/硬件编程

    • 发布日期:2020-05-28
    • 文件大小:647168
    • 提供者:EL KA
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