搜索资源列表
systolic
- 脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systolic）的乘法器
Copy-of-Systolic-Architecture-to-convert-colour-t
- the paper presents efficient colour conversion algorithm for fpga implementations
Systolic_Array
- Multiplier using systolic array
SDRAM-USING
- Field programmable gate arrays (FPGAs) are emerging in many areas of high performance computing, either as tailor made signal processor, embedded algorithm implementation, systolic array, software accelerator or application specific architecture. FPG
TABLOO
- Field programmable gate arrays (FPGAs) are emerging in many areas of high performance computing, either as tailor made signal processor, embedded algorithm implementation, systolic array, software accelerator or application specific architecture. FPG
XILINX-JTAG-PROGRAMER
- Field programmable gate arrays (FPGAs) are emerging in many areas of high performance computing, either as tailor made signal processor, embedded algorithm implementation, systolic array, software accelerator or application specific architecture. FPG
behavioral
- This is a code for systolic multiplier,it can be modified for more lenght in data input
systolic
- 实现QR_RLS算法,基于fpga 的非线性功放的dpd实现-realize QR_RLS
systolic--matrix-inversion
- DSP算法架构及设计，内容为基于systolic的上三角矩阵求逆电路的实现，里面有详尽的MATLAB/SIMULINK 仿真模型，及HDL代码和在modelsim中的仿真程序，非常不错的。-Architecture and design of DSP algorithms, based on systolic upper triangular matrix inverse circuit to achieve detailed MATLAB/SIMULINK model and the HDL
Homework4
- 4x4矩阵乘法，使用pipeline结构，可以在AutoESL中综合出Verilog，并在System Generator中测试通过。-Matrix multification in systolic way for AutoESL synthesis
systolic_mul_D8_M193
- 193位8段的GF(2m)域上的Digit-Serial 脉动结构(Systolic)的乘法器-a 193bit GF(2m) Ditital-Serial Systolic Multiplier
matrix-inversion
- 基于Systolic的上三角矩阵求逆的实现，含有详细的verilog代码，并给出详细的注释-upper triangular matrix inversion