搜索资源列表
DIVIDER
- 大家好，我是复旦大学的研究生。本资源是一个基于VHDL语言的M位除以N位的除法器。其中M/N ，商M位，余数是N位的。以Moim设计验证和验证。压缩包里有除法器的源文件和testbench。可加入工程，直接测试。鄙人测试都是无错误的。愿尊驾下载后，积极评价，以便于相互交流，学习。O(∩_∩)O谢谢.2015年5月7日于芬兰，图尔库。-Hello everyone, I am a graduate student at Fudan University. This resource is base
QPSK
- 这是关于QPSK调制解调的VerilogHDL语言的代码，还有用Modelsim仿真的工程文件。testbench都已经写好了。-This is the QPSK modulation and demodulation of VerilogHDL language code, as well as with Modelsim simulation project file. testbench have been written.
verilog_code_for_double_fpu
- 64位FPU，内含testbench，已经通过验证仿真。-64-bit FPU, embedded testbench, simulation has been validated.
iic
- i2c接口的功能实现代码，用VERILOG编写，并附有testbench.-i2c interface function implementation code, written in VERILOG, along with testbench
VHDL_Multiplier
- 三种 VHDL 实现乘法器的方法，可以用于学习FPGA的时序、组合电路，同时附带了 TestBench 程序-Three kinds of methods to achieve multiplier in VHDL, with TestBench
sdram_5
- SDRAM的verilog描述，包含顶层设计，测试平台代码，精确描述-SDRAM is verilog descr iption, including top-level design, testbench code, an accurate descr iption of
ADC_AD7490
- THIS PROJECT IMPLEMENTED ON VITERX 4 FPGA and THE COMPLETE SOURCE FILES testbench, design file UCF file are there and THIS ADC is maily configured with SPI protocol interface SPI CLK,SPI DATA, SPI LE, the SPEED OF OPERATION OF SPI CLK is 10 MHZ
OFDM_Convolution
- 自己写的卷积码，能实现仿真结果,有testbench文件-Write your own convolution code, simulation results can be achieved
OWIRE
- OWIRE verilog代码，实现了单总线上的通信传输的HDL顶层，子模块设计和testbench内容-The code of 1wire bus
tst_bench_top
- I2C控制总线的测试平台testbench，用于验证I2C主机冲击交互的正确性-I2C control bus test platform testbench, used to verify the correctness of the interaction I2C master impact
sdram_latest.tar
- SDRAM的控制代码，包含文档说话和testbench测试代码-SDRAM control code, including documents speak and testbench test code
LEDWATER
- 跑马灯/流水灯代码，实现左右移和幂布式流水四种模式的循环变换，并包含testbench文件。-Marquee/water lamp code, move around to achieve the water and power distributed four modes of loop transformations, and includes testbench files.
uart
- Atmega 328 UART clone with testbench, cannot be synthesized to gates
Spread-Spectrum-Analyzer
- Spread-Spectrum-Analyzer in verilog with testbench
ddr2_controller
- A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.
debouncer_vhdl
- RTL and testbench implementations for a switch debouncer with support for multiple switches, written in VHDL.
RGB2YUV_TB
- 将RGB颜色空间转换为YUV颜色空间的testbench，用verilog写得，可以测试看看。-Convert RGB color space to YUV color space testbench, written in verilog, can test and see.
abs_mode
- abs_mode 2-complement souce and testbench code
dct_parallel.tar
- paralel DCT hardware in verilog with testbench
trafficlight
- VHDL实现红绿灯，multisim测试通过，可直接烧录到FPGA板上进行测试,带testbench-VHDL realize traffic lights, multisim tested, can be burned directly to the FPGA board for testing, with testbench