This project was undertaken to produce a low power FIR filter for inclusion in a VHDL target library. The design was completed using OrCAD s Capture CIS, from this the VHDL code has been extracted. This method has allowed complete testing of the syst

BIST for RAMs using ASTRA: Transparent Built-In Self Test (BIST) schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric transparent BIST skips the signature prediction phase required in traditional