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uart
- ARN7核s3c44b0串口程序源码,包括FIFO,非FIFO多模式的接收发送.
UART.使用FPGA的FIFO，状态机
- 使用FPGA的FIFO，状态机，乒乓操作等实现了异步UART。,The use of FPGA-FIFO, state machine, ping-pong operation to achieve the asynchronous UART.
uart8.zip
- 使用Libero提供的异步通信IP核实现UART通信，并附带仿真程序。UART设置为1位开始位，8位数据位，1位停止位，无校验。且UART发送自带2级FIFO缓冲，占用FPGA面积很小。,Libero provided the use of asynchronous communication IP core implementation UART communications, and incidental simulation program. UART is set to 1 to sta
uartfifo
- 基于FPGA的串口发送源代码，通过FIFO能够发送一段字符串。-FPGA-based serial port source code, a string can be sent through the FIFO.
uart_fifo
- avr单片机串口先进先出实例程序，这是个人在实际项目中应用的一个例子，还有是定时器的使用方法-Examples of single-chip FIFO serial avr procedures, which are individual projects in the actual application of an example are also the use of timer
LM3S_UART
- 《LM3S系列CPU高性能串口驱动程序》 现在很多ARM7芯片已经使用了Cotex-M3内核，我开始接触这东西是从周立功的LM3S1138开始的。周立功提供的1138串口例程基本不具有实用性…… 该驱动程序在利用LM3S系列CPU自身FIFO的同时，利用环形缓冲区构建了软件层的Buffer，采用中断方式进行Buffer读写，效率高，运行稳定，可用于透传、网关等各种大数据流量的场合。程序包含头文件，注释详尽；基于Stellaris外设驱动库编写，方便移植。并支持485通信，串口初始化数据自
uart_EP3C16_FIFO
- Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings.
usb
- USB 到 UART 协议转换程序 [简易的 - 少量的FIFO] 目标 MCU :AT90S2313-10-USB to UART protocol conversion process [simple- a small number of FIFO] target MCU: AT90S2313-10
int_uart8051
- UART realization for at89c5131 with FIFO and interrupts.
NIOS_JTAG_UART
- FPGA开发板上的JTAG——UART完成的工程设计，包括CPU内核设计合软件设计-FPGA development board JTAG- UART completed the engineering design, including the CPU core design combined software design
FIFOSRC
- DSP uart窗口通信中的一种通信格式，FIFO模式的一个小程序-dsp serial communication uart communication first in first out-FIFO mode
FIFO-UART
- 基于ARM7-LM3S1138的FIFO方式的UART数据传输代码-ARM7-LM3S1138 based on the FIFO mode of UART data transmission code
fifoed_avalon_uart9.1_applicaton
- 用于Altera Avalon总线的、具有FIFO缓冲的Uart数据串口IP核以及应用于Nios2的、真正可运行的、容易移植的C代码。-Fifoed avalon uart IP core and C code for the IP core.
uart
- Also the USART automatically senses the start of transmission of RX line and then inputs the whole byte and when it has the byte it informs you(CPU) to read that data from one of its registers. The USART of AVR is very versatile and can be setup
fifouart_latest.tar
- vhdl fifo uart core datasheet
UART-FIFO
- easy arm1138 UART-FIFO 收发程序-easy arm1138 UART-FIFO receive program
UART
- 基于FPGA的UART设计，包含接收模块，发送模块，FIFO模块-UART FPGA-based design, including the receiver module, sending module, FIFO module
UART-fifo-memcpy
- S3C2440上的UART读取实现使用fifo缓冲区,并且用memcpy实现，加快运行速度-S3C2440 UART fifo memcpy
uart
- 带有fifo的功能模块，具有发送模块和接收功能模块(The function module with FIFO has transmitting module and receiving function module)
fifo
- 一个简单的FIFO实现，基于STM32的UART+DMA方式。(A simple FIFO implementation, based on the STM32 UART+DMA approach.)