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DDSandVFO.rar
- Simple 0 to 6 MHz DDS VFO using Analog Devices AD9832,Simple 0 to 6 MHz DDS VFO using Analog Devices AD9832
quaddecoder_verilog_ise11.2_used_09042010
- Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descr ipted in the Constrained file quad.ucf. To use them, y
dds
- 外网下的相仿制的关于ad9851的dds vfo的资料-The phase of imitation outside the network on the dds vfo data ad9851
dds-12864
- 这个是想仿制的用lcd12864显示屏显示的dds vfo-This is to copy the display with the dds vfo lcd12864
dds-vfo4.0
- 用pic单片机控制lcd1602显示的dds vfo-With pic microcontroller control lcd1602 display dds vfo