搜索资源列表
project_PmodKYPD
- 用Digilent公司BASYS3开发板和PmodKYPD模块，实现对按键的检测。程序基于VIVADO 2015.4，语言为verilog。(Digilent's BASYS3 development board and PmodKYPD module are used to detect keystrokes. The program is based on VIVADO 2015.4 and the language is verilog.)
Single_cpu
- 单周期CPU自己课程大作业做的，亲测好用，verilog语言，适用vivado(Single cycle CPU course to do, pro - use, Verilog language, suitable for vivado)
vivado2017_xpogod
- vivado 2017 开发软件下载，需要的朋友可以拿去使用，(Vivado 2017 development software downloads, the need of friends can be used)
at7_ex01
- 8个LED执行流水灯。流水灯依次循环点亮。基于vivado平台编写的Verilog代码(The 8 LED executes the flow light. The flow light is turned on and out in turn. Verilog code based on vivado platform)
at7_ex03
- 使用FPGA内部的PLL产生时钟，计数器循环计数驱动LED闪烁。基于vivado平台编写的Verilog代码(Use FPGA's internal PLL to generate clock, counter cycle counting drive LED flicker. Verilog code based on vivado platform)
at7_ex04
- 通过LED闪烁控制器的代码，使用Vivado工具配置定义一个IP核，在用户工程中可随意添加这个IP核作为设计的一部分，如同Vivado自带的IP核一样方便调用和集成。(Through the code of the LED scintillation controller, the Vivado tool is configured to define a IP core, and the IP kernel can be added as part of the design at rando
mips16
- 来自openhec平台，完整的mips16cpu设计。未添加工程，需自己手动建立工程添加文件，仅供参考。(mips16 cpu.no vivado project.It's just for teaching.If you want to learn more about it, please search for OpenHec.)
ARM_SOC
- ARM最小系统，vivado或ISE综合后下载至FPGA板子上可以做ARM用，包含连接在AHB总线上的RAM和ROM，ARM内核引出JTAG接口，可以连接调试器用keil-MDK进行调试！(ARM minimum system, vivado or ISE integrated download to the FPGA board can be used as ARM, including the RAM and ROM connected to the AHB bus, the ARM ker
pencode83b
- 8-3优先编码器，在vivado中的项目，可直接打开.xpr，版本vivado2017.4(8-3encodervivado2017.4)
Xilinx_Vivado_Design_Suite_HLx_Editions_2018.2
- vivado 2018.2 license
cordic
- 基于verilog HDL的cordic算法FPGA实现。省去繁琐的乘法开方计算。IDE为vivado 2014( U57FA u4E8Everilog HDL u7684cordic u7B97 u6CD5FPGA u5B9E u73B0 u3002 u7B1 u53BB u7E1 u7410 u7684 u4E58 u6CD5 u5F00 u65B9 u8BA1 u7B97 u300BIDE u4E3Avivado 2014)
CIC
- 包括地址产生单元、数据查询单元（可以重新初始化rom中的数据，由matlab产生.coe文件替换）、积分单元、抽取单元、梳状滤波单元，对于初学者很有帮助(Including address generation unit, data query unit (data can be re-initialized in rom, generated by matlab. COE file replacement), integration unit, extraction unit, comb fi
rx_module
- 接收机的顶层模块构建,对需要参考的朋友有一定的帮助(The construction of the top module of the receiver is helpful to friends who need reference.)
shifter
- 基于vivado的Xilinx的FPGA其移位寄存器代码(Xilinx's FPGA shift register code based on vivado)
down_up_dds
- 在Vivado下完成AD输入到下变频的功能，频率可配置，通用化设计。(The function of AD input to down conversion is completed under Vivado, and the frequency is configurable and universal design.)
09_ddr3_test
- 利用vivado的MIG控制器来实现DDR3的读写(Using vivado's MIG controller to realize DDR3's read and write)
defog
- 图像去雾算法FPGA实现，使用xilinx Vivado开发环境(Image dehazing algorithm FPGA implementation using xilinx Vivado development environment)
AT426-BU-98000-r0p0-00rel0
- Cortex-M3软核,适用于Vivado 2018.2以上版本(Cortex-M3 IP,suitable for the Vivado 2018.3 or later)
VHDLcounter
- VHDL，四位counter，用Vivado写的，可运行，可模拟，可仿真，可写入硬件里，四个指示灯会每一秒闪一次。
vivado
- 用中规模MSI基本逻辑功能模块 实现关模比较器（要求分别使用中规模和语言实现）： 功能要求：它的输入是两个8位无符号二进制整数X和Y，以及一个控制信号S；输出信号为1个8位无符号二进制整数Z。输入输出关系为：当S=1时， Z=min(X,Y)；当S=0时， Z=max(X,Y)。(Modeling comparator is implemented by using basic logic function modules of medium-scale MSI (medium-scale an